Synchronizing signal detecting circuit

• US 4,719,523 A
• Filed: 04/30/1986
• Issued: 01/12/1988
• Est. Priority Date: 05/28/1985
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kutaragi, Ken
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US06/857,258
• Time in Patent Office: 622 Days
• Field of Search: 360/51, 360/48, 360/40, 369/59, 375/119, 375/120
• US Class Current: 360/51
• CPC Class Codes: G11B 20/1254 for mixed data, i.e. continuous and discontinuous data
• CPC Class Codes: G11B 27/3027 used signal is digitally coded
• CPC Class Codes: H04L 7/08 the synchronisation signals recurring cyclically
• CPC Class Codes: H04N 5/935 Regeneration of digital synchronisation signals

Abstract

A synchronizing signal detecting circuit for a digital data reproducing apparatus has a reproducing device connected to a magnetic head which scans a recording medium for deriving digital signals, a phase locked loop circuit connected to the reproducing device for generating a clock signal based on the derived digital signals, a synchronizing counter for generating synchronizing timings by counting the clock signal, a plurality of synchronizing pattern detecting circuits connected to the reproducing device for detecting synchronizing patterns included in the digital signals, and a logic circuit connected to the plurality of synchronizing pattern detecting circuits for supplying an initialize pulse to the synchronizing counter upon detecting successive synchronizing patterns in the digital signals by the plurality of synchronizing pattern detecting circuits.

Claims

1. A synchronizing signal detecting circuit for digital data reproducing apparatus comprising:

reproducing means for deriving digital signals from a storage medium;

phase locked loop means connected to said reproducing means for generating clock signals based on said derived digital signals;

synchronizing counter means for generating synchronizing timings by counting said clock signals;

a plurality of synchronizing pattern detecting means connected to said reproducing means for detecting synchronizing patterns included in said digital signals; and

logic circuit means connected to said plurality of synchronizing pattern detecting means for supplying an initialize pulse to said synchronizing counter means upon detecting successive synchronizing patterns in said digital signals at said plurality of synchronizing pattern detecting means.

2. A synchronizing signal detecting circuit as in claim 1;

wherein said plurality of synchronizing pattern detecting means includes at least a series-connected first pattern detector and a second pattern detector, and pattern coincidence outputs are supplied from said first and second pattern detectors to said logic circuit means.

3. A synchronizing signal detecting circuit as in claim 2;

wherein said logic circuit means includes an AND gate, and said synchronizing counter means includes a reset terminal to which an output of said AND gate is connected.

4. A synchronizing signal detecting circuit as in claim 1;

wherein said digital signals include n-bit channel data converted from m-bit source data, where n and m are integers and n is larger than m.

5. A synchronizing signal detecting circuit as in claim 4;

wherein said digital signals derived from said reproducing means are converted from said n-bit channel data to said m-bit source data based on said synchronizing timings derived from said synchronizing counter means.

6. A synchronizing signal detecting circuit as in claim 5;

wherein said m-bit source data includes a sector synchronizing interval having a plurality of sector synchronizing sections, each of which includes number data changing successively.

7. A synchronizing signal detecting circuit as in claim 6;

further comprising number data counter means which is loaded with said number data of the sector synchronizing sections when the number data are correct.

8. A synchronizing signal detecting circuit as in claim 7;

wherein said number data counter means is supplied with a clock signal derived from said synchronizing timings, and supplies a frame start signal.

9. A synchronizing signal detecting circuit as in claim 1;

wherein said digital signals substantially comprise a plurality of sectors, and each sector includes a preamble section, a plurality of frames and post-amble section.

10. A synchronizing signal detecting circuit as in claim 9;

wherein said successive synchronizing patterns included in said digital signals are positioned at said preamble section included in each of said sectors.