Method and apparatus for limiting bus utilization

• US 4,719,567 A
• Filed: 04/29/1982
• Issued: 01/12/1988
• Est. Priority Date: 04/29/1982
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Whittington, Charles L., Zolnowsky, John
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/373,206
• Time in Patent Office: 2,084 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 370/85, 340/825.5
• US Class Current: 710/117
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

A bus master is prevented from utilizing a communication bus during a current sample interval if the utilization rate of the communication bus during the immediately preceeding sample interval exceeded a selected limit.

Claims

1. A method for limiting the utilization of a communication bus by a bus master, comprising the steps of:

determining the utilization rate of the bus during a first sample interval; and

disabling the bus master from utilizing the bus during a succeeding second sample interval if the utilization rate during the preceeding first sample interval was determined to be above a selected limit.

2. The method of claim 1 wherein the bus master arbitrates for the use of the bus, and wherein the step of disabling the bus master is further characterized as preventing the bus master from arbitrating for the use of the bus during the succeeding second sample interval if the utilization rate during the preceeding first sample interval was determined to be above the selected limit.

3. The method of claim 1 or 2 wherein the first sample interval comprises a predetermined number of clock cycles of the bus master, and wherein the utilization rate is determined as the ratio of the number of the clock cycles during which the bus is utilized during the first sample interval to the number of the clock cycles comprising the first sample interval.

4. A bus utilization rate limiter for limiting the utilization of a communication bus by a bus master, comprising:

means coupled to said bus, for determining the utilization rate of the bus during a first sample interval; and

means coupled to said bus master and to said means for determining the bus utilization rate, for disabling the bus master from utilizing the bus during a succeeding second sample interval if the utilization rate during the preceeding first sample interval was determined to be above a selected limit.

5. The bus utilization rate limiter of claim 4 wherein the bus master arbitrates for the use of the bus, and wherein the means for disabling the bus master are further characterized as means for preventing the bus master from arbitrating for the use of the bus during the succeeding second sample interval if the utilization rate during the preceeding first sample interval was determined to be above the selected limit.

6. The bus utilization rate limiter of claim 4 or 5 wherein the first sample interval comprises a predetermined number of clock cycles of the bus master, and wherein the utilization rate is determined as the ratio of the number of the clock cycles during which the bus is utilized during the first sample interval to the number of the clock cycles comprising the first sample interval.