Optimization network for the decomposition of signals

• US 4,719,591 A
• Filed: 11/07/1985
• Issued: 01/12/1988
• Est. Priority Date: 11/07/1985
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.), Calif Institute of Technology
• Inventors: Tank, David W., Hopfield, John J.
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/795,789
• Time in Patent Office: 796 Days
• Field of Search: 364/807, 364/300, 364/131, 364/900, 364/828, 364/829, 364/800, 364/808, 364/811, 364/815
• US Class Current: 708/801
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G06N 3/044 Recurrent networks, e.g. Hopfield networks
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: H03M 1/125 Asynchronous, i.e. free-running operation within each conversion cycle
• CPC Class Codes: H03M 1/42 Sequential comparisons in series-connected stages with no change in value of analogue signal

Abstract

A network comprising analog amplifiers with a resistive interconnection matrix that connects each amplifier output to the input of all other amplifiers. The connections embodied in the matrix are achieved with conductances whose values are computed in accordance with the set of decomposition functions for which the solution is sought. In addition to the specified connectivity implemented. Further included is a second matrix that connects externally applied voltages to the amplifier inputs via resistors whose values are also computed in accordance with the set of decomposition functions for which the solution is sought. Still further and in accordance with another aspect of the invention, means are included for varying the amplifier gains from an initial low value to an ultimately high value in the process of arriving at a solution to an applied problem.

Claims

1. A circuit for determining a best fit to input signals with a selected set of basis functions ε

_k, which are signal functions of a preselected variable, said circuit comprising;

an N plurality of gain-providing amplifiers, where N is a chosen number with each amplifier A_i having an input terminal and output terminal; and

conductance devices of conductance value T_ij, with each conductance device connecting said output terminal of amplifier A_i to the input terminal of amplifier A_j, i and j being subscripts that denote a particular of said amplifiers and conductance devices wherein

each of said conductance values T_ij is related to the dot product of the i^th basis function ε

_i and the j^th basis function ε

_j.

2. The circuit of claim 1 further comprising a current I_i injected into said input terminal of amplifier A_i, with said current I_i being related to the dot product of said input signals with ε

_i and to the dot product of ε

_i with itself.

3. The circuit of claim 1, wherein each of said amplifiers includes a gain control port, and said circuit further comprises means for varying the gain of said amplifiers.

4. The circuit of claim 1, further comprising means for setting the gain of said amplifiers at a low level and increasing said gain to its ultimate high level to obtain a stable output of said circuit.

5. A circuit for decomposing an input signal comprising one or more input voltages in terms of a selected set basis functions ε

_k, that are signal functions of a preselected variable, said circuit including, a plurality of gain-providing amplifiers A_i where i is an index designating a particular amplifier in said plurality of amplifiers, said amplifier A_i having input and output terminals and said circuit including a first interconnection matrix for connecting the output terminal of each amplifier A_i to the input terminal of each other amplifier A_j via a conductance device having a conductance value T_ij characterized by;

a second interconnection matrix for coupling a portion of a preselected bias voltage and a portion of said input voltages to said input terminal of each of said amplifiers.

6. The circuit of claim 5, further comprising means for varying the gain of said amplifiers.

7. The circuit of claim 5 wherein said conductance values T_ij are related to a dot product of said basis functions, and wherein said second interconnection matrix connects said preselected bias voltage and said input voltages to said input terminals via conductances that are related to said basis functions.

8. The circuit of claim 5 wherein said conductance values T_ij are related to a dot product of ε

_i and ε

_j, where ε

_i and ε

_j are members of the set of nonorthogonal functions ε

_k and wherein said second interconnection matrix connects said preselected bias voltage to said input terminal of each said amplifier A_i via a conductance that is related to the dot product of ε

_i with itself, and connects each of said input voltages to said input terminal of each said amplifier A_i via a conductance that is related to said ε

_i.

9. An A/D converter responsive to an input voltage comprising:

a plurality of amplifiers A_i having input and output terminals and a first interconnection matrix for connecting the output terminal of each amplifier A_i to the input terminal of each other amplifier A_j via a conductance device of conductance value T_ij that connects the output terminal of amplifier A_i to the input terminal of amplifier A_j, i and j being indices that designate particular amplifiers and conductances;

a second interconnection matrix for connecting a preselected applied bias voltage -v and said input voltage to said input terminal of each of said amplifiers;

wherein the value of each T_ij is set to -2.sup.(i+j) for i≠

j and to 0 for i=j and wherein said second interconnection matrix connects said preselected bias voltage to said input terminal of amplifier A_i via a conductance having the value 2.sup.(2i-1) /v and connects said inputs voltage to said input terminal of amplifier A_i via a conductance having the value 2ⁱ.

10. A circuit comprising a plurality of amplifiers, with each amplifier i having an input capacitor C, an input resistor ρ

and developing an output signal V_i in response to an input signal u_i at the amplifier'"'"'s input terminal, and a connection matrix for interconnecting the output signal V_i of each amplifier i to said input terminal of each of said amplifiers through a set of conductances of conductance value T_ij, where j designates amplifier j to whose input T_ij is connected, i and j being indices that designate particular amplifiers and conductances characterized by;

an input signal I_i being injected into said input terminals of each amplifier i;

said amplifiers including means for controlling the magnitude of the gain developed by said amplifiers;

the value of each conductance T_ij selected for the nature of the decisional operation intended to satisfy the circuit equation of motion ##EQU14## and;

said circuit including means for varying said gain of said amplifiers.