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Memory with improved column access

  • US 4,719,602 A
  • Filed: 02/07/1985
  • Issued: 01/12/1988
  • Est. Priority Date: 02/07/1985
  • Status: Expired due to Term
First Claim
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1. In a semiconductor memory device having:

  • a multiplicity of data storage locations arranged in rows and columns, said storage locations being addressed by a plurality of binary address signals;

    said address signals being divided into row address signals and column address signals;

    said column address signals being further divided into low and high order column address signals;

    a set of sense amplifiers for latching and transferring data to and from a selected row of said data storage locations; and

    data input and output buffers for receiving and transmitting data;

    the improvement comprising;

    a plurality of secondary sense amplifiers for latching and transferring data to and from selected ones of said sense amplifiers, said sense amplifiers being selected in accordance with said high order column address signals; and

    decoder means responsive to said low order column address signals for selecting one of said secondary sense amplifiers and connecting it to said data input and output buffers.

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