Memory with improved column access
First Claim
1. In a semiconductor memory device having:
- a multiplicity of data storage locations arranged in rows and columns, said storage locations being addressed by a plurality of binary address signals;
said address signals being divided into row address signals and column address signals;
said column address signals being further divided into low and high order column address signals;
a set of sense amplifiers for latching and transferring data to and from a selected row of said data storage locations; and
data input and output buffers for receiving and transmitting data;
the improvement comprising;
a plurality of secondary sense amplifiers for latching and transferring data to and from selected ones of said sense amplifiers, said sense amplifiers being selected in accordance with said high order column address signals; and
decoder means responsive to said low order column address signals for selecting one of said secondary sense amplifiers and connecting it to said data input and output buffers.
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Accused Products
Abstract
A semiconductor memory device having an improved system for randomly accessing a preselected set of memory locations. The invention includes a set of "secondary sense amplifiers" which act as a high speed buffer between the memory'"'"'s normal sense amplifiers and the memory'"'"'s data input and output buffers. The secondary sense amplifiers are connected to selected ones of the sense amplifiers in accordance with a first predefined subset of the memory'"'"'s column address signals. A decoder circuit, which is directly responsive to a second predefined subset of the column address signals, selects one of the secondary sense amplifiers and connects it to the memory'"'"'s data input and output buffers. Since the decoder is directly responsive to the second predefined subset of the column address signals and does not need to latch in new address values after the detection of an address signal transition, all the secondary sense amplifiers can be accessed much faster than the other data storage locations in the memory.
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Citations
8 Claims
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1. In a semiconductor memory device having:
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a multiplicity of data storage locations arranged in rows and columns, said storage locations being addressed by a plurality of binary address signals;
said address signals being divided into row address signals and column address signals;
said column address signals being further divided into low and high order column address signals;a set of sense amplifiers for latching and transferring data to and from a selected row of said data storage locations; and data input and output buffers for receiving and transmitting data; the improvement comprising; a plurality of secondary sense amplifiers for latching and transferring data to and from selected ones of said sense amplifiers, said sense amplifiers being selected in accordance with said high order column address signals; and decoder means responsive to said low order column address signals for selecting one of said secondary sense amplifiers and connecting it to said data input and output buffers. - View Dependent Claims (2, 3, 4, 5)
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6. In a method of operating a dynamic memory device;
- said device having;
a multiplicity of data storage locations arranged in rows and columns, said storage locations being addressed by a plurality of binary address signals;
said address signals being divided into row address signals and column address signals;
said column address signals being further divided into low and high order column address signals;a set of sense amplifiers for latching and transferring data to and from a selected row of said data storage locations; and data input and output buffers for receiving and transmitting data; the steps of; providing a plurality of secondary sense amplifiers; transferring data between said secondary sense amplifiers and selected ones of said sense amplifiers, said sense amplifiers being selected in accordance with said high order column address signals; and selecting one of said secondary sense amplifiers in accordance with said low order column address signals and connecting it to said data input and output buffers. - View Dependent Claims (7, 8)
- said device having;
Specification