System bus means for inter-processor communication

• US 4,719,622 A
• Filed: 03/15/1985
• Issued: 01/12/1988
• Est. Priority Date: 03/15/1985
• Status: Expired due to Term

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: Wang Laboratories Incorporated
• Inventors: Whipple, David L.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Marcelo, Melvin
• Application Number:
  US06/712,492
• Time in Patent Office: 1,033 Days
• Field of Search: 370/89, 370/88, 370/85, 340/825.5, 340/825.05, 364/200, 364/900
• US Class Current: 370/438
• CPC Class Codes: G06F 13/37 using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004

Abstract

A system bus and bus interface apparatus for connecting components in a data processing system having a plurality of non-memory and memory components. The system bus has the following sets of lines; A first plurality of lines carries a plurality of codes specifying a plurality of memory operations involving communications between a non-memory component and a memory component and a single code specifying an interprocessor communication between two non-memory components. A second plurality of lines carries an address in a memory component when the code on the first plurality of lines specifies a memory operation and a target address, an interprocessor communication type, and in some cases, a message, when the code on the first plurality of lines specifies an interprocessor communication. A third plurality of lines carries signals indicating the status of a memory operation, a fourth plurality of lines carries signals indicating the status of an interprocessor communication, a fifth plurality of lines carries data in memory operations and in certain interprocessor communications, and a sixth plurality of lines determines which of the components presently has access to the bus. Memory communications may specify read and write operations, but interprocessor communications may specify only operations in which the source component provided data to the destination component.

Claims

1. A system bus for coupling components of a data processing system which includes a memory component and other components and carrying a communication between at least two of the components,

the system bus comprising:

a first plurality of lines for carrying first codes including

a plurality of memory operation codes specifying a plurality of types of memory communications having an other component as a source and the memory component as the recipient and

a single inter-processor communication code specifying a non-memory communication having one of the other components as a source and another thereof as a recipient;

a second plurality of lines which,

when the first plurality of lines specifies one of the memory communication types, carries an address in the memory component and,

when the first plurality of lines specifies a non-memory communication, carries one of a plurality of type codes specifying a plurality of types of non-memory communications and one of a plurality of recipient address codes specifying an other component as recipient;

a third plurality of lines for carrying signals specifying the status of a current memory communication; and

a fourth plurality of lines for carrying signals specifying the status of a current non-memory communication.

2. A system bus as set forth in claim 1 wherein:

the system bus includes a fifth plurality of lines for carrying data;

the plurality of types of memory communications includes

write communications wherein the source component provides data on the fifth plurality of lines to the memory component to be written at the address specified by the second plurality of lines and

read communications wherein the source component receives data stored at the address specified by the second plurality of lines from the memory component on the fifth plurality of lines; and

the plurality of types of non-memory communications includes types of communications wherein the source component provides data to the recipient component on the fifth plurality of lines, but does not include communications wherein the recipient component provides data to the source component.

3. A system bus as set forth in claim 2 wherein:

the memory component stores data in memory words divisible into half words and bytes;

the types of write communications include

a write byte communication for writing a byte,

a write half word communication for writing a half word,

a write word communication for writing a word, and

a write double word communication for writing two words;

the types of read communications include

a read word communication for reading a word,

a read double word communication for reading two words,

a read quad word communication for reading four words, and

a read octal word communication for reading eight words; and

the address on the second plurality of line specifies the portion of a word, the word, or the sequence of words being read or written.

4. A system bus as set forth in claim 2 wherein:

the other components include

a central processing unit for processing data,

a system bus interface unit, and

a plurality of satellite processing units coupled to the

system bus interface unit; and

the types of non-memory communications include

types wherein the recipient component is the central processing unit,

types wherein the recipient component is the system bus interface unit, and

types wherein the recipient component is one of the satellite processing units.

5. A sytem bus as set forth in claim 4 wherein:

the types wherein the recipient component is the central processing unit include

a first I/O interrupt communication indicating that an I/O operation finished without error; and

a second I/O interrupt communication indicating that an error occurred during an I/O operation.

6. A system bus as set forth in claim 4 wherein:

the types wherein the recipient component is one of the satelite processing units include

a message transfer communication;

a data transfer communication; and

a reset recipient satellite processing unit communication.

7. A system bus as set forth in claim 1 and wherein:

the third plurality of lines includes

a wait line for carrying a wait signal indicating that the source component is to wait for completion of the memory operation specified in the communication;

a busy line for carrying a busy signal indicating that the memory component is busy; and

a valid memory access line for carrying a valid memory access signal indicating that the memory operation resulted in a valid memory access.

8. A system bus as set forth in claim 1 and wherein:

the fourth plurality of line includes

an acknowledgement line for carrying an acknowledgement signal indicating that the recipient component received the communication and

a target busy line for carrying a target busy signal indicating that the recipient component is busy.

9. A system bus as set forth in claim 1 wherein:

the codes specifying the non-memory communication further include a fifth code specifying a message in certain of the communications.

10. A system bus as set forth in claim 1 wherein:

the system bus includes a fifth plurality of lines for carrying data; and

certain of the non-memory communications include data transferred from the source to the recipient on the fifth plurality of lines.

11. A system bus as set forth in claim 1 and further including:

a system bus priority line for carrying an access signal indicating which component of those which presently can be sources of communications may have access to the system bus; and

a lock line for carrying a lock signal indicating that one source component is retaining access to the system bus.

12. System bus interface apparatus for coupling a component other than a memory component of a data processing system which includes both memory and other components to a system bus which has

a first plurality of lines for carrying first codes including a plurality of memory operation codes specifying a plurality of types of memory communications having an other component as a source and the memory component as the recipient and a single inter-processor communication code specifying a non-memory communication having one of the other components as a source and another thereof as a recipient,

a second plurality of lines which, when the first plurality of lines specifies a memory communication, carry an address in the memory component and, when the first plurality of lines specifies a non-memory communication, carry one of a plurality of type codes specifying a plurality of types of non-memory communications and one of a plurality of recipient address codes specifying an other component as recipient, and

a third plurality of lines for carrying signals specifying the status of any non-memory communication,

the system bus interface apparatus comprising:

control means coupled to the first plurality of lines, the second plurality of lines, and the third plurality of lines corresponding to the interprocessor communication code on the first plurality of lines and to a recipient component address on the second plurality of lines specifying the component containing the system bus interface by producing a first signal indicating the receipt of the communication and second signals on the third lines specifying the status of the communication;

means coupled to the second plurality of lines and responsive to the first signal for retaining the type code in response to the first signal; and

processing means coupled to the type code retention means for receiving and interpreting the retained type code.

13. The system bus interface apparatus as set forth in claim 12 wherein:

the second plurality of lines further carries a message code specifying a message in certain of the non-memory communications;

the type code retaining means further retains the message code; and

the type code interpreting means interprets the message code as well as the type code in the certain non-memory communications.

14. The system bus interface apparatus as set forth in claim 12 wherein:

the third lines include an acknowledgement line for carrying an acknowledgement signal indicating that the component to which the bus interface apparatus belongs has received the communication and a recipient busy line for carrying a recipient busy signal indicating that the component is presently busy; and

the control means further responds to the interprocessor communication code on the first plurality of lines and to a recipient component address on the second plurality of lines specifying the component to which the system bus interface apparatus belongs by producing the busy signal on the busy line when the component to which the system bus interface apparatus belongs is busy.

15. The system bus interface apparatus as set forth in claim 14 wherein:

the control means further provides the inter-processor communication code to the first plurality of lines when the non-memory component is a source of an inter-processor communication;

the system bus interface apparatus further includes communication providing means coupled to the second plurality of lines and to the processing means for receiving a type code of the plurality of type codes and a recipient address code of the plurality of recipient address codes from the processing means and providing the type code and the recipient address code to the second plurality of lines when the non-memory component is a source of an inter-processor communication; and

the control means further includes means coupled to the third plurality of lines for receiving and responding to the acknowledgement and busy signals produced by the control means in the recipient non-memory component specified by the recipient address code in response to the type code and recipient address code from the source.

16. The system bus interface apparatus as set forth in claim 15 wherein:

the system bus further includes

a system bus priority line which carries an access signal indicating which component of those which presently can be sources of communications may have access to the system bus and

a lock line which carries a lock signal indicating that one source component is retaining access to the system bus;

the control means is further responsive to the access signal and the lock signal when the access signal indicates that the non-memory component may be the source component presently making a communication and the lock line does not indicate that another non-memory component is retaining access by providing the interprocessor communication code on the first plurality of lines and the contents of the communication providing means to the second plurality of lines; and

the communication providing means is further coupled to the lock line and provides the lock signal when the source component presently making a communication is retaining access to the system bus.

17. The system bus interface apparatus as set forth in claim 12 and wherein:

the system bus further includes a fourth plurality of lines for carrying signals specifying the status of any memory communication;

the control means further provides a memory operation code of the plurality of memory operation codes on the first plurality of lines when the non-memory component is a source of a memory communication; and

the communication providing means provides an address in the memory component on the second plurality of lines when the non-memory component is a source of a memory communication; and

the control means is further coupled to the fourth plurality of lines and is responsive to the signals thereon.

18. The system bus interface apparatus as set forth in claim 17 and wherein:

the fourth plurality of lines includes a wait line for carrying a wait signal indicating that the non-memory source component is to wait for completion of the memory operation,

a memory component busy line for carrying a memory component busy signal indicating that the memory component is busy, and

a valid memory access line for carrying a valid memory access signal indicating that the memory access performed in the memory operation was valid.

19. The system bus interface apparatus as set forth in claim 17 wherein:

the system bus further includes

a system bus priority line which carries an access signal indicating which component of those which presently can be sources of communications may have access to the system bus and

a lock line which carries a lock signal indicating that one source component is retaining access to the system bus;

the control means is further responsive to the access signal and the lock signal when the access signal indicates that the non-memory component may be the source component presently making a communication and the lock line does not indicate that another non-memory component is retaining access by providing the interprocessor communication code on the first plurality of lines and the contents of the communication providing means to the second plurality of lines; and

the communication providing means is further coupled to the lock line and provides the lock signal when the source component presently making a communication is retaining access to the system bus.

20. The system bus interface apparatus as set forth in claim 17 wherein:

the system bus includes a fifth plurality for carrying data;

the system bus interface apparatus further includes data providing and receiving means coupled to the fifth plurality of lines for receiving data from the fifth plurality of lines and providing data to the fifth plurality of lines;

the plurality of memory operation codes includes read codes specifying memory read operations and write codes specifying memory write operations;

the plurality of non-memory communication type codes includes type codes specifying communications wherein the source component provides data to the recipient component but not type codes specifying communications wherein the recipient component provides data to the source component; and

the data providing and receiving means provides data to the fifth plurality of lines when the control means provides a memory operation code specifying a write operation and when the control means provides the inter processor communication code and the communication providing means provides a type code specifying a communication which provides data to the recipient component and receives data from the fifth plurality of lines when the control means provides a memory operation code specifying as read operation.

21. System bus interface apparatus as set forth in claim 20 wherein:

the memory component stores data in memory words divisible into half words and bytes;

the types of write communications include

a write byte communication for writing a byte,

a write half word communication for writing a half word,

a write word communication for writing a word, and

a write double word communication for writing two words;

the types of read communications include

a read word communication for reading a word,

a read double word communication for reading two words,

a read quad word communication for reading four words, and

a read octal word communication for reading eight words;

and the address on the second plurality lines specifies the word,

the portion of a word, or the sequence of words being read or written.

22. System bus interface apparatus as set forth in claim 21 wherein:

the other components include

a central processing unit for processing data,

a system bus interface unit, and

a plurality of satellite processing units coupled to the system bus; and

the types of non-memory communications include

types wherein the recipient components is the central processing unit,

types wherein the recipient component is the system bus interface unit, and

types wherein the recipient component is one of the satellite processing units.

23. System bus interface apparatus as set forth in claim 22 wherein:

the types wherein the recipient component is one of the satellite processing units include

a message transfer communication;

a data transfer communication; and

a reset recipient satellite processing unit communication.

24. System bus interface apparatus for coupling a memory component of a data processing system which includes both memory and other components to a system bus which has

a first plurality of lines for carrying first codes including a plurality of memory operation codes specifying a plurality of types of memory communication having an other component as a source and the memory component as the recipient and a single inter-processor communication code specifying a non-memory communication having one of the other components as a source and another thereof as a recipient,

a second plurality of lines which, when the first plurality of lines specifies a memory communication, carry an address in the memory component and, when the first plurality of lines specifies a non-memory communication, carry one of a plurality of type codes specifying a plurality of types of non-memory communications and one of a plurality of recipient address codes specifying an other component as recipient,

a third plurality of lines for carrying signals specifying the status of any memory communication,

a fourth plurality of lines for carrying signals specifying the status of any non-memory communication, and

a fifth plurality of lines for carrying signals indicating data,

the system bus interface apparatus comprising:

control means coupled to the first plurality of lines and the third plurality of lines for responding to a memory operation code by producing a first signal indicating receipt of the communication and status signals on the third lines specifying the status of the communication, the third lines including

a wait line for carrying a wait signal indicating that the non-memory component which was the source of the memory operation code is to wait for completion of the specified memory operation,

a busy line for carrying a busy signal indicating that the memory component is busy and that the source non-memory component is to retry specified memory operation, and

a valid memory access line for carrying a valid memory access signal indicating that the speicified memory operation had valid results;

address receiving means coupled to the second plurality of lines and responsive to the first signal for retaining the address in response to the first signal; and

data providing and receiving means coupled to the fifth plurality of lines for receiving data to be stored at the location specified by the retained address when the memory operation code indicates a write operation and for providing data from the location specified by the retained address when the memory operation code indicates a read operation.