Microprocessor capable of stopping its operation at any cycle time
First Claim
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1. A microprocessor comprising:
- (1) a logic circuit for effecting a desired logic operation;
(2) a timing pulse generator circuit for generating at least a first timing pulse and a second timing pulse;
(3) an input flip-flop circuit, an output of which is connected to an input of said logic circuit;
(4) an output flip-flop circuit, an input of which is connected to an output of said logic circuit;
(5) means coupled to said timing pulse generator circuit for controlling supply an non-supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit, respectively, in response to a first input signal for indicating a test mode and a second input signal for indicating a clock advancing operation;
(6) first memory means, an output of which is connected to control said controlling means to supply said first timing pulse to said input flip-flop circuit;
(7) second memory means, an output of which is connected to control said controlling means so as to supply said second timing pulse to said output flip-flop circuit; and
(8) means for inputting test data into said input flip-flop circuit during said test mode; and
wherein said control means includes means for supplying said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit, respectively, during a normal mode of operation;
wherein said control means includes means for stopping said supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit in response to said first input signal and for supplying said test data to said input flip-flop circuit from said inputting means during a test mode of operation; and
wherein said control means includes means for controlling the supply and non-supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit in response to said second input signal, said output of said first memory means and said output of said second memory means during an advanced mode of operation.
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Abstract
Herein disclosed is a method of controlling a microprocessor in accordance with the present invention characterized in that, when the microprocessor for executing a microprogram in accordance with clock cycles Φ1 and Φ2 receives a command (i.e., STOP signal) for stopping a normal operation from the outside, a freezing signal (i.e., FRZ signal) synchronizing with the clock cycles is generated to bring the operation being executed into a stopped state.
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2 Claims
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1. A microprocessor comprising:
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(1) a logic circuit for effecting a desired logic operation; (2) a timing pulse generator circuit for generating at least a first timing pulse and a second timing pulse; (3) an input flip-flop circuit, an output of which is connected to an input of said logic circuit; (4) an output flip-flop circuit, an input of which is connected to an output of said logic circuit; (5) means coupled to said timing pulse generator circuit for controlling supply an non-supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit, respectively, in response to a first input signal for indicating a test mode and a second input signal for indicating a clock advancing operation; (6) first memory means, an output of which is connected to control said controlling means to supply said first timing pulse to said input flip-flop circuit; (7) second memory means, an output of which is connected to control said controlling means so as to supply said second timing pulse to said output flip-flop circuit; and (8) means for inputting test data into said input flip-flop circuit during said test mode; and wherein said control means includes means for supplying said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit, respectively, during a normal mode of operation; wherein said control means includes means for stopping said supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit in response to said first input signal and for supplying said test data to said input flip-flop circuit from said inputting means during a test mode of operation; and wherein said control means includes means for controlling the supply and non-supply of said first timing pulse and said second timing pulse to said input flip-flop circuit and said output flip-flop circuit in response to said second input signal, said output of said first memory means and said output of said second memory means during an advanced mode of operation. - View Dependent Claims (2)
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Specification