Fuse selection of predecoder output
First Claim
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1. A defect tolerant memory device, comprising:
- an array of memory elements arranged in rows and columns, each of said rows having a control input for activation thereof, said rows addressable by an external address having n bits received at terminals of said device, said array having 2n rows;
a row of redundant memory elements disposed adjacent said array and having a redundant control input for activation thereof;
a plurality of predecode means each for receiving m adjacent bits of the n bits of said address from said terminals and predecoding the m bits from a binary format into one of 2m mutually exclusive output;
final decode means for receiving the 2m outputs from each of said predecode means and outputting 2n mutually exclusive decode outputs, each of said 2n decode outputs interfaced with said control input of one of the rows in said array;
deactivation means for selectively deactivating one of said 2n decode outputs from said final decode means; and
redundant decode means for receiving the 2m outputs from each of said predecode means and being selectively programmable to activate the redundant control input to said redundant row of memory elements when said address from said terminals corresponding to the deactivated one of the rows in said array is input to said predecode means.
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Abstract
A fuse selectable decoder for a redundant row of memory elements in an array includes a redundant decode select circuit (38) for receiving predecoder inputs from predecode lines (28), (30), (32) and (34). The predecode lines are output from predecoders (20), (24) and (26) which decode an eight bit address word. The redundant decode select circuit (38) is programmed by fuse select circuit (40) that selects the address of a defective one of the rows of memory elements in an array (10). The redundant decode select circuit (38) selects one line out of each of the predecode lines (28), (30), (32) and (34) for input to an AND gate (112) for selecting the redundant row (12).
28 Citations
18 Claims
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1. A defect tolerant memory device, comprising:
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an array of memory elements arranged in rows and columns, each of said rows having a control input for activation thereof, said rows addressable by an external address having n bits received at terminals of said device, said array having 2n rows; a row of redundant memory elements disposed adjacent said array and having a redundant control input for activation thereof; a plurality of predecode means each for receiving m adjacent bits of the n bits of said address from said terminals and predecoding the m bits from a binary format into one of 2m mutually exclusive output; final decode means for receiving the 2m outputs from each of said predecode means and outputting 2n mutually exclusive decode outputs, each of said 2n decode outputs interfaced with said control input of one of the rows in said array; deactivation means for selectively deactivating one of said 2n decode outputs from said final decode means; and redundant decode means for receiving the 2m outputs from each of said predecode means and being selectively programmable to activate the redundant control input to said redundant row of memory elements when said address from said terminals corresponding to the deactivated one of the rows in said array is input to said predecode means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A defect tolerant memory device, comprising:
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an array of memory elements arranged in rows and columns, each of said rows having a control input for activation thereof, said rows addressed by an external row address applied to terminals of said device having n bits, said array having 2n rows; a row of memory elements disposed adjacent said array and having a redundant control input for activation thereof; a plurality of predecoders each for receiving m adjacent bits of the n address bits from said terminals and predecoding the m bits from a binary format into one of 2m mutually exclusive outputs; final decode means associated with each of the control inputs for activation thereof, each of said final decode means for receiving a select one of the 2m outputs from each of said predecoders and outputting a decode signal to activate the associated one of said rows, said decode signal occurring when the logic state of the select ones of the 2m outputs are equal to a predetermined logic state; deactivation means associated with each of said final decode means for inhibiting output of said decode signal, said deactivation means selected to deactivate a defective one of said rows; select means associated with each of said predecoders for selecting one of the 2n outputs associated therewith, said select means in a normally unselected state; programming means for determining which of said associated 2m predecode outputs is selected by each of said select means; and redundant decode means associated with said redundant row control input for receiving the outputs of said select means and outputting a redundant decode signal when the logic state of the outputs of each of said select means is equal to a predetermined logic state. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification