Method and apparatus for clearing the memory of a video computer

• US 4,720,819 A
• Filed: 12/30/1983
• Issued: 01/19/1988
• Est. Priority Date: 12/30/1983
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Guttag, Karl M., Pinkham, Raymond
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/567,038
• Time in Patent Office: 1,481 Days
• Field of Search: 365/189, 365/128, 365/238, 365/219, 365/220
• US Class Current: 365/219
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence

Abstract

In a video computer system and the like having a bit-mapped RAM component including a shift register, an improved method is provided for rapidly clearing the RAM in order to prepare the system to receive new input data. More particularly, a preselected number of predetermined data bits corresponding to the number of columns in the RAM is serially shifted into the register. Thereafter, the contents of the shift register are progressively shifted into each of the rows in the RAM until all rows are filled.

Claims

1. A method of initializing a video-type system or the like having processor means, memory means, and a video display, said memory means having a plurality of memory cells arranged in rows and columns and having serial register means coupled to said columns, comprising:

deriving a plurality of predetermined data signals in said processor means, storing said derived signals serially in said serial register means in a predetermined sequence,

selecting one of said rows of memory cells in said memory means, and

transferring each of said stored data signals from said serial register means to corresponding ones of said cells in said selected row.

2. The method described in claim 1, further including transferring each of said stored data signals to said selected row in corresponding ones of said columns of memory cells in said array.

3. The method described in claim 2, further including simultaneously transferring all of said stored data signal to all of the columns for said selected row of memory cells in said array.

4. The method described in claim 3, further comprising

generating a plurality of first command signals, and

deriving said sequence of predetermined data signals as a function of said first command signals.

5. The method described in claim 4, further comprising

generating a row address signal in said system, and

selecting said row of memory cells as a function of said row address signal in said system.

6. the method described in claim 5, further comprising

generating a write signal in said system, and

transferring said stored data signals to said selected row of memory cells as a function of said write signal in said system.

7. The method described in claim 6, further including the step of storing said transferred data signals in said selected row of memory signals as a function of said write signal in said system.

8. The method described in claim 7, wherein said transferred data signals are all stored simultaneously in said selected row of memory cells as a function of said write signal in said system.

9. The method described in claim 8, wherein said derived data signals are al transferred and stored simultaneously in said selected row of memory cells as a function of said write signal in said system.

10. A method of initializing a computer system having processor means, semiconductor memory means, and a video display, said memory means having a plurality of memory cells arranged in rows and columns interconnectable in parallel with serial register means comprising

deriving a plurality of predetermined data signals in said processor means corresponding in number to said plurality of solumns of memory cells of the memory means,

storing said derived data signals in said register means,

selecting one of said rows of memory cells, and

transferring said data signals from said register means to said corresponding cells in said selected row.

11. The method described in claim 10, further comprising, shifting said derived data signals into said shift register.

12. The method of claim 11, further comprising

generating a sequence of first command signals in said processor means, and

serially transferring and storing said derived data signals into said register means in response to said sequence of first command signals.

13. The method described in claim 12, wherein all of said data signals in said register means are transferred simultaneously to said memory cells in said selected row.

14. The method described in claim 13, further comprising

generating a second sequence of second command signals, and

selecting said one of said rows of memory cells in response to said second command signals.

15. The method described in claim 14, wherein said second command signals correspond to row address control signals in said computer system.

16. The method described in claim 15, further comprising

generating a third command signal, and

transferring said stored data signals simultaneously into said corresponding memory cells in said selected row in response to said third command signal.

17. The method described in claim 16, wherein said third command signal corresponds to the "write" control signal in said computer system.

18. The method described in claim 17, wherein said first command signal corresponds to clock control signals in said computer system.

19. A method of creating and updating video display means in a system having processor means, video display means, semiconductor and memory means holding bit-mapped data for said display means, comprising:

writing a predetermined sequence of N data bits into a memory array in said memory means having M rows and N columns of read and write memory cells,

by the steps of shifting said sequence of N data bits serially into register means, and thereafter

addressing said M rows in succession and writing said N data bits in parallel into each of said M rows in succession.

20. A method of initializing a bit-mapped memory of a computer-controlled video display system or the like, comprising:

deriving a plurality of predetermined data signals,

serially storing said derived signals in register means of the memory,

selecting a portion of said memory, and thereafter

transferring said serially stored signals from said register means into said selected portion of said memory in parallel.

21. The method described in claim 20, further comprising,

sequentially selecting different portions of said memory, and

sequentially transferring said signals into said sequentially selected portions of said memory in parallel.