CMOS current switching circuit

• US 4,721,866 A
• Filed: 11/21/1985
• Issued: 01/26/1988
• Est. Priority Date: 11/21/1985
• Status: Expired due to Fees

• Current Assignee: Digital Equipment Corporation (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Chi, Kuang K., Sullivan, Barbara M.
• Primary Examiner(s): Zazworsky, John
• Assistant Examiner(s): Wambach, M. R.
• Application Number:
  US06/800,644
• Time in Patent Office: 796 Days
• Field of Search: 307/584, 307/585, 307/304, 307/270, 307/451
• US Class Current: 326/86
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A CMOS current steering switch circuit includes a switch formed of a pair of transistors of one conductivity type having a source terminal connected to a node to which a constant current source is also connected. The drain terminals of the transistors comprise the switch circuit'"'"'s output terminals. The transistor'"'"'s gate terminals are controlled by a pair of buffers comprising transistors of the other conductivity type that receive differential input signals that control the switch circuit. The buffers limit the voltage swings of the control signals applied to the gate terminals so that the transistors comprising the switch are not both off at the same time.

Claims

1. A switch circuit for receiving differential input signals and transmitting output signals in response thereto comprising:

A. current steering switch means comprising two MOS transistors each including a drain terminal, the drain terminals of both said MOS transistors being connected to a current input node means, a source terminal, each source terminal of said respective MOS transistors being connected to a respective output terminal and a gate terminal,

B. current source means connected to said current input node means for supplying a constant current to said current input node means; and

C. a pair of buffer means each receiving one of the differential input signals and each connected to the gate terminal of one of said MOS transistors, each said buffer means generating a control signal for controlling the respective MOS transistor, each said buffer means includes pull-up transistor means having a drain terminal connected to a positive power supply, pull-down transistor means having a source terminal connected to ground, and resistor means connected between the source terminal of the pull-up transistor means and the drain terminal of the pull-down transistor means, the respective control signal being taken from the drain terminal of said pull-down transistor means, each of the differential input signals controlling the gate of the pull-up transistor means of one said buffer means and the gate of the pull-down transistor means of the other of said buffer means, the resistor means reducing the positive level of the respective control signal so that the gate-to-drain voltage levels of the MOS transistors do not turn them both off when the input signals are switching signal levels.

2. A switch circuit as defined in claim 1 wherein, in each said buffer means the resistor means comprises a transistor whose gate terminal is connected to its drain terminal, the transistor'"'"'s drain terminal being connected to the source terminal of the respective buffer'"'"'s pull-up transistor means and the transistor'"'"'s source terminal being connected to the drain terminal of the respective buffer'"'"'s pull-down transistor means.