Real-time pulse processor

• US 4,721,958 A
• Filed: 10/23/1985
• Issued: 01/26/1988
• Est. Priority Date: 10/23/1985
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Corporation
• Original Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Jenkin, Keith R.
• Primary Examiner(s): Tubbesing, T. H.
• Assistant Examiner(s): Barron, Jr., Gilberto
• Application Number:
  US06/790,699
• Time in Patent Office: 825 Days
• Field of Search: 342/13, 342/20, 342/192, 342/195, 307/518, 307/524, 328/108, 328/109, 328/110, 328/139, 328/140, 328/119, 375/94, 364/517, 364/528, 324/78 F, 324/78 R, 382/16, 382/17, 382/36, 382/37, 382/38, 377/54, 377/50, 370/112
• US Class Current: 342/13
• CPC Class Codes: G01R 23/02 Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
• CPC Class Codes: G01R 29/02 Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
• CPC Class Codes: G01S 7/021 Auxiliary means for detecting or identifying radar signals or the like, e.g. radar jamming signals

Abstract

Apparatus, which first de-interleaves a signal, that comprises a plurality of interleaved pulse trains, into its constituent pulse trains and then identifies the emitter which transmitted each pulse train, is described herein. Specifically, this apparatus comprises a folded shift register which performs the de-interleaving. The folded shift register comprises a plurality of serially connected identical "active" cells, each of which detects a pulse occurring at a particular group pulse repetition interval (PRI) and, in an embodiment described herein, ascertains the inter-pulse PRI for each detected pulse for use in identifying an emitter. One or more processors analyze the group and inter-pulse PRI data, provided by the folded shift register, in order to identify each emitter.

Claims

1. A system for de-interleaving an input signal, having successively occurring input pulses, into a plurality of constituent pulse trains and for identifying at least one emitter that produced an associated one of said constitutent pulse trains, wherein the improvement comprises:

de-interleaving means, responsive to said input signal, for determining the pulse repetition interval of each of said input pulses, and for routing each of said input pulses to a respective one of a plurality of "hit" output leads, wherein each of said "hit" output leads corresponds to a different group pulse repetition interval, and wherein said de-interleaving means comprises

n-1 separate cells, each of said cells having first and second shift elements, in said first shift elements are serially interconnected together to form a first leg of a shift register and said second shift elements are serially interconnected together to form a second leg of a shift register, and said input pulses are applied as input to a first end of said first leg,

a central cell, having a shift element and connected to said first and second legs, wherein the central cell shift element receives, as input thereto, bits shifted out from a second end of said first leg and applies, to an input of said second leg and to a central cell output lead, bits shifted out of said central cell, and

a logic circuit, associated with each of a plurality of said n-1 cells to form a corresponding plurality of "active" cells, wherein each of said logic circuits is connected to the output of the first and second shift elements located in a respective cell and to said central cell output lead and provides an associated one of said "hit" output leads, and wherein each logic circuit detects the occurrence of a triplet pulse comprising separate pulses having a predetermined group pulse repetition interval and appearing in said first and second shift elements in the respective cell and on said central cell output lead

2. The system in claim 1 wherein the plurality of "active" cells is comprised of n-m serially connected "active" cells, where m is an integer and lies within the range of 0<

m≦

n.

3. The system in claim 2 wherein at least an ith one of said "active" cells further comprises means, serially interconnected between the output of the second shift element in said ith cell and the input to the second shift element in an i+1st one of said "active" cells and operates in response to a triplet pulse detected by said logic circuit, for inhibiting the input pulse appearing, at the output of the second shift element and which formed part of a triplet pulse, from propagating from the ith cell through said second leg to the second shift element in the i+1st cell.

4. The system in claim 3 wherein each of the "active" cells further comprises said inhibiting means and all of said inhibiting means are substantially identical.

5. The system in claim 4 wherein each logic circuit further comprises means, responsive to each triplet pulse detected therein, for gating one of said input pulses which formed part of that triplet pulse to the associated "hit" output lead.

6. The system in claim 5 wherein the logic circuit further comprises means for ascertaining an interval of time occurring between successive triplet pulses detected by said logic circuit.

7. The system in claim 6 wherein the ascertaining means comprises a counter which counts the number of clock intervals occurring between said successive triplet pulses and provides an output value indicative of said count, whereby the output value represents the interpulse pulse repetition interval for the input pulse substantially simultaneously appearing on the associated "hit" output lead.

8. The system in claim 5 wherein the logic circuit further comprises means for detecting the occurrence of both a triplet pulse and at least one additional condition before gating one of the input pulses to the associated "hit" output lead.

9. The system in claim 8 wherein the logic circuit further comprises a counter which is loaded with a predefined numerical value after the occurrence of each triplet pulse detected by that logic circuit, wherein the numerical value is then decremented at the occurrence of each successive clock interval occurring between the detection of that triplet pulse and an immediately subsequent triplet pulse, and wherein said additional condition is satisfied if said counter reaches a zero count substantially simultaneously with the occurrence of the subsequent triplet pulse.

10. The system in claim 7 wherein said de-interleaving means further comprises:

a third shift element associated with each of said n-1 cells and connected to the logic circuit associated with each "active" cell, wherein all of said third shift elements are serially interconnected to form a separate shift register, and wherein, in response to the detection of a triplet pulse within any "active" cell, a pulse is provided as input to the third element associated with that "active" cell by the logic circuit associated therewith,

a third row output lead which receives the bits shifted out from an end of said separate shift register, and

wherein each of said associated logic circuits further comprises means, connected to said third row output lead and responsive to the occurrence of a triplet pulse and a pulse simultaneously occurring on the third row output lead, for gating one of the input pulses comprising said triplet pulse onto the associated "hit" output lead.

11. The system in claims 7, 9 or 10 wherein the de-interleaving means is further comprised of:

means, responsive to a pulse shifted out of said second end of the first leg, for extending the duration thereof by at least two clock intervals and for applying the resulting extended pulse to a half step output lead,

a first one of said logic circuits, associated with at least the ith one of said "active" cells, for detecting a first triplet pulse comprising separate pulses occurring on the outputs of said first and second shift elements located within said ith cell and on the central cell output lead,

a second one of said logic circuits, also associated with said ith cell, for detecting a second triplet pulse comprising separate pulses occurring at the output of said first shift element located within said ith cell, on said half step output lead and at the output of the second shift element located in the i+1st cell, wherein said first and second logic circuits are substantially identical.

12. The system in claim 11 wherein the first logic circuit further comprises means, responsive to said first triplet pulse, for providing one of the input pulses on the associated "hit" output lead;

and said second logic circuit further comprises means, responsive to said second triplet pulse, for providing one of the input pulses comprising said second triplet pulse on another associated "hit" output lead, whereby the second logic circuit detects triplet pulses spaced at least 1/2 clock interval later than those detected by the first logic circuit so that the resolution of the de-interleaving means is effectively doubled without increasing the number of cells.

13. The system in claims 7, 9 or 10 wherein the de-interleaving means is further comprised of:

means, responsive to a pulse appearing at any one of various pre-defined locations in said first and second legs, for providing an extended pulse and for applying the extended pulse to a jittered output lead,

a logic circuit, associated with at least the ith one of said "active" cells, for selectively detecting a non-jittered triplet pulse comprising separate pulses substantially simultaneously occurring on the outputs of said first and second shift elements located within said ith cell and on the central cell output lead, or a jittered triplet pulse comprising separate pulses occurring at the output of said first and second shift elements located within the ith cell and on the jittered output lead.

14. The system in claims 7, 9 or 10 wherein the de-interleaving means is further comprised of means for clocking all the shift elements comprising said second leg at least 1/2 clock intervals after all the shift elements for the first leg are clocked.

15. The system in claim 1 including:

identifying means, connected to said "hit" output leads, for separately analyzing the input pulses appearing on at least one of said "hit" output leads to discern any repetitive pattern existant therein and thereby partially identify the emitter which corresponds to the input pulses appearing on said one output.

16. The system in claim 7 including:

identifying means, connected to said "hit" output leads for separately analyzing the input pulses appearing on at least one of said "hit" output leads to discern any repetitive pattern existant therein and thereby partially identify the emitter which corresponds to the input pulses appearing on said one output.

17. The system in claims 15 or 16 wherein the identifying means comprises means for accumulating the input pulses appearing on at least an ith one of the associated "hit" output leads during a predetermined time interval.

18. The system in claim 17 wherein the accumulating means further comprises means for separately totalizing the input pulses appearing on the ith "hit" output lead and occurring at each different inter-pulse pulse repetition interval value that said ith one of the "active" cells is capable of resolving.

19. The system in claim 18 wherein the identifying means further comprises means, responsive to said totalized pulse counts and to a pulse descriptor word associated with at least one of the input pulses that comprise the discerned pattern, for identifying the emitter which transmitted a de-interleaved pulse train depicted by said pattern.

20. The system in claim 18 wherein the totalizing means further comprises a table for storing totalized pulse counts for each possible inter-pulse pulse repetition interval value that can be resolved by the ith cell.

21. The system in claim 20 wherein the identifying means further comprises means for generating a temporal histogram for the ith cell in response to the totalized pulse counts stored in the table associated with the ith cell.

22. The system in claim 21 wherein the identifying means further comprise means for analyzing the totalized pulse counts for at least the ith cell in order to discern any repetitive pattern existant therein.

23. The system in claim 22 wherein the identifying means further comprises at least one processor for totalizing the pulse counts for at least the ith cell and another processor for analyzing the totalized pulse counts for at least the ith cell.

24. The system in claim 23 wherein the identifying means further comprises means, responsive to said totalized pulse counts and to a pulse descriptor word associated with at least one of the input pulses that comprise the discerned pattern, for identifying the emitter which transmitted a de-interleaved pulse train depicted by said pattern.

25. In a system for de-interleaving an input signal, having successively occurring input pulses, into a plurality of constituent pulse trains and for identifying at least one emitter that produced an associated one of said constituent pulse trains, wherein the improvement comprises:

de-interleaving means, responsive to said input signal, for determining the pulse repetition interval of each of said input pulses, and for routing each of said input pulses to a respective one of a plurality of "hit" output leads, wherein each of said outputs corresponds to a different group pulse repetition interval, wherein said de-interleaving means comprises;

n-1 separate cells, each of said cells having first and second shift elements, said first shift elements are serially interconnected together to form a first leg of a shift register and said second shift elements are serially interconnected together to form a second leg of a shift register, and said input pulses are applied as input to a first end of said first leg,

a central cell, having a shift element and connected to said first and second legs, wherein the central cell shift element receives, as input thereto, bits shifted out from a second end of said first leg and applies, to an input of said second leg and to a central cell output lead, bits shifted out of said central cell, and

a substantially identical logic circuit, associated with n-m of said n-1 cells (where m is an integer within the range of 0<

m≦

n) to form n-m "active" cells, wherein each of said logic circuits is connected to the output of the first and second shift elements located in a respective "active" cell and to said central cell output lead and provides an associated one of said "hit" output leads, and wherein each logic circuit detects the occurrence of a triplet pulse having a pre-determined group pulse repetition interval and comprising separate pulses appearing in said first and second shift elements in the respective "active" cell and on said central cell output lead; and

identifying means, connected to said "hit" output leads, for separately analyzing the input pulses appearing on at least one of said "hit" output leads to discern any repetitive pattern existant therein and thereby partially identify the emitter corresponding to the input pulses appearing on said one output, wherein said identifying means comprises means for accumulating the input pulses appearing on at least an ith one of the associated "hit" output leads during a pre-determined time interval.

26. The system in claim 25 wherein each of the "active" cells further comprises means, serially interconnected between the output of the second shift element in the ith cell and the input to the second shift element in the i+1st cell and operates in response to a triplet pulse detected by said logic circuit, for inhibiting the input pulse appearing, at the output of the second shift element and which formed part of a triplet pulse, from propagating from said ith cell through said second leg to the second shift element in the i+1st cell.

27. The system in claim 26 wherein each logic circuit further comprises means, responsive to each triplet pulse detected therein, for gating one of said input pulses which formed part of that triplet pulse to the associated "hit" output lead.

28. The system in claim 27 wherein the logic circuit further comprises means for ascertaining an interval of time occurring between successive triplet pulses detected by said logic circuit.

29. The system in claim 28 wherein the ascertaining means comprises a counter which counts the number of clock intervals occurring between said successive triplet pulses and provides an output value indicative of said count, whereby the output value represents the inter-pulse pulse repetition interval for the input pulse substantially simultaneously appearing on the associated "hit" output lead.

30. The system in claim 29 wherein the de-interleaving means is further comprised of:

a third shift element associated with each of said n-1 cells and connected to the logic circuit associated with each "active" cell, wherein all of said third shift elements are serially interconnected to form a separate shift register, and wherein, in response to the detection of a triplet pulse within any "active" cell, a pulse is provided as input to the third element associated with that "active" cell by the logic circuit associated therewith,

a third row output lead which receives the bits shifted out from an end of said separate shift register, and

wherein each of said associated logic circuits futher comprises means, connected to said third row output lead and responsive to the occurrence of a triplet pulse and a pulse simultaneously occurring on the third row output lead, for gating one of the input pulses comprising said triplet pulse onto the associated "hit" output lead.

31. The system in claims 29 or 30 wherein the de-interleaving means is further comprised of:

means, responsive to a pulse shifted out of said second end of the first leg, for extending the duration thereof by at least two clock intervals and for applying the resulting extending pulse to a half step output lead,

a first one of said logic circuits, associated with at least the ith one of said "active" cells, for detecting a first triplet pulse comprising separate pulses occurring on the outputs of said first and second shift elements located within said ith cell and on the central cell output lead,

a second one of said logic circuits, also associated with said ith cell, for detecting a second triplet pulse comprising separate pulses occurring at the output of said first shift element located within said ith cell, on said half step output lead and at the output of the second shift element located in the i+1st cell, wherein said first and second logic circuits are substantially identical.

32. The system in claims 29 or 30 wherein the de-interleaving means is further comprised of:

means, responsive to a pulse appearing at any one of various pre-defined locations in said first and second legs, for providing an extended pulse and for applying the extended pulse to a jittered output lead,

a logic circuit, associated with at least the ith one of said "active" cells, for selectively detecting a non-jittered triplet pulse comprising separate pulses occurring on the outputs of said first and second shift elements located within said ith cell and on the central cell output lead, or a jittered triplet pulse comprising separate pulses occurring at the output of said first and second shift elements located within the ith cell and on the jittered output lead.

33. The system in claim 25 wherein the accumulating means further comprises:

means for separately totalizing the input pulses appearing on the ith "hit" output lead and occurring at each different inter-pulse pulse repetition interval value said ith cell is capable of resolving, and

a table for storing totalized pulse counts for each of said different inter-pulse pulse repetition intervals.

34. The system in claim 33 wherein the identifying means further comprises means for generating a temporal histogram for the ith cell in response to the totalized pulse counts stored in the table associated with the ith cell.

35. The system in claims 33 or 34 wherein the identifying means further comprises:

means, for analyzing the totalized pulse counts for at least the ith cell in order to discern any repetitive pattern existant therein, and

means, responsive to each discerned pattern and to a pulse descriptor word associated with at least one of the detected pulses that comprise the discerned pattern, for identifying the emitter which transmitted a de-interleaved pulse train depicted by said pattern.

36. A method for use in a system for de-interleaving an input signal, having successively occurring input pulses, into a plurality of constituent pulse trains and for identifying at least one emitter that produced an associated one of said contituent pulse trains, wherein the method comprises:

a de-interleaving step wherein the pulse repetition interval of each of said pulses in said input signal is determined and each of said pulses in said input signal is determined and each of said input pulses is routed to a respective one of a plurality of "hit" outputs, wherein each of said "hit" outputs corresponds to a different group pulse repetition interval, and wherein said de-interleaving step includes the steps of;

forming n-1 separate cells, wherein each of said cells contains at least first and second shift elements,

linking said first shift elements together for form a first leg of a shift register,

linking said second shift elements together to form a second leg of a shift register,

applying said input pulses as input to a first end of said first leg,

forming a central cell, having a shift element linked to said first and second legs,

applying bits shifted out from a second end of said first leg to an input of the central cell shift element,

routing bits shifted out of aid central cell shift element both to an input of said second leg and to a central cell output, and

detecting, in response to the output of the first and second shift elements located in a respective cell and to input pulses appearing on said central cell output, the occurrence of a triplet pulse having a pre-determined group pulse repetition interval and comprising separate pulses appearing at the outputs of said first and second shift elements in the respective cell and on said central cell output lead.

37. The method in claim 36 wherein the detecting step further includes the step of detecting triplets in only n-m serially aligned cells, where m is an integer within the range of 0<

m≦

n, so as to form n-m "active" cells.

38. The method in claim 37 wherein the de-interleaving step further includes the step of:

inhibiting the input pulse appearing, at the output of the second shift element and which formed part of a triplet pulse, from propagating from an ith one of said "active" cells through said second leg to the second shift element in an i+1st one of said n-1 cells.

39. The method in claim 38 wherein the detecting step includes the step of gating, in response to each detected triplet pulse, one of the input pulses which formed part of the detected triplet pulse to the associated "hit" output.

40. The method in claim 39 wherein the detecting step includes the step of ascertaining an interval of time occurring between successive detected triplet pulses.

41. The method in claim 40 wherein the ascertaining step includes the steps of counting the number of clock intervals occurring between said successive triplet pulses and providing an output value indicative of said count, whereby the output value represents the interpulse pulse repetition interval for the input pulse substantially simultaneously appearing on the associated "hit" output.

42. The method in claim 41 wherein the detecting step further includes the stpes of:

loading a counter with a pre-defined numerical value after the occurrence of each detected triplet pulse,

decrementing the numerical value at the occurrence of each successive clock interval occurring between the detection of that detected triplet pulse and a next subsequently detected triplet pulse, and

gating one of the input pulses which comprises the detected triplet pulse to the associated "hit" output if the counter reaches a zero count substantially simultaneously with the occurrence of the subsequently detected triplet pulse.

43. The method of claim 42 wherein said de-interleaving step includes the steps of:

forming a third shift element associated with each of aid n-1 cells,

linking said third shift elements together to form a separate shift register,

providing, in response to the detection of a triplet pulse within any cell, a pulse as input to the third element associated with that cell,

applying bits shifted out from an end of said separate shift register to a third row output lead, and

gating, in response to the occurrence of a triplet pulse and a pulse simultaneously occurring on the third row output lead, one of the input pulses comprising the detected triplet pulse onto the associated "hit" output.

44. The method in claim 43 wherein the de-interleaving step further includes the steps of:

extending the duration of any input pulse shifted out of the second end of the first leg by at least two clock intervals,

applying the resulting extedned pulse to a half step output,

detecting a first triplet pulse comprising separate pulses occurring on the outputs of said first and second shift elements located within an ith one of said "active" cells and on the central cell output,

providing, in response to the occurrence of the first triplet pulse, one of the input pulses comprising the first triplet pulse on the associated "hit" output,

detecting a second triplet pulse comprising separate pulses occurring at the output of said first shift element located within said ith cell, on said half step output and at the output of the second shift element located in the i+1st cell, wherein said second triplet occurs at least 1/2 clock interval later than said first triplet pulse, and

providing, in reponse to the occurrence of the second triplet pulse, one of the input pulses comprising the second triplet pulse on another associated "hit" output.

45. The method in claim 36 including:

an identifying step wherein the pulses appearing on at least one of said "hit" outputs is separately analyzed to discern any repetitive pattern existant there in order to partially identify the emitter which corresponds to the input pulses appearing on said one "hit" output.

46. The method in claim 40 including:

an identifying step wherein the pulses appearing on at least one of said "hit" outputs is separately analyzed to discern any repetitive pattern existant therein in order to partially identify the emitter which corresponds to the input pulses appearing on said one "hit" output.

47. The method in claims 41, 43 or 44 wherein the de-interleaving step includes the steps of:

providing, in response to a pulse appearing at any one of various pre-defined locations in said first and second legs, an extended pulse and for applying the extended pulse to a jittered output lead,

selectively detecting a non-jittered triplet pulse comprising separate pulses occurring on the outputs of said first and second shift elements located within said ith cell and on the central cell output lead, or a jittered triplet pulse comprising separate pulses occurring at the output of said first and second shift elements located with in the ith cell and on the jittered output lead.

48. The method in claims 41, 43 or 44 wherein the de-interleaving step further includes the step of clocking all the shift elements comprising said second leg at least 1/2 clock intervals after all the shift elements for the first leg are clocked.

49. The method in claims 45 or 46 wherein the identifying step further includes the step of accumulating the input pulses appearing on at least an ith one of the associated "hit" outputs during a pre-determined time interval.

50. The method in claim 49 wherein the accumulating step further includes the steps of:

separately totalizing the input pulses appearing on the ith "hit" output and occurring at each different inter-pulse pulse repetition interval value that said ith one of the "active" cells is capable of resolving, and

storing, in a table, the totalized pulse counts for each possible inter-pulse pulse repetition interval value that can be resolved by the ith cell.

51. The method in claim 48 wherein the identifying step further includes the steps of:

analyzing the totalized pulse counts for at least the ith cell in order to discern any repetitive pattern existant therein, and

identifying, in response to each discerned pattern and to a pulse descriptor word associated with at least one of the input pulses that comprise the discerned pattern, the emitter which corresponds to a de-interleaved pulse train depicted by said pattern.

52. The method in claim 50 wherein the identifying step includes the step of generating a temporal histogram for the ith cell in response to the totalized pulse counts stored in the table associated with the ith cell.

53. The method in claim 52 wherein the identifying step further includes the steps of:

analyzing the totalized pulse counts for at least the ith cell in order to discern any repetitive pattern existant therein, and

identifying, in response to each discerned pattern and to a pulse descriptor word associated with at least one of the input pulses that comprise the discerned pattern, the emitter which corresponds to a de-interleaved pulse train depicted by said pattern.