Compiler for evaluating Boolean expressions

• US 4,722,071 A
• Filed: 04/19/1985
• Issued: 01/26/1988
• Est. Priority Date: 04/19/1985
• Status: Expired due to Term

• Current Assignee: Schneider Automation Incorporated (Schneider Electric SE)
• Original Assignee: Pertron Controls Corporation
• Inventors: Rosen, David B., Jones, Gary A., Gates, Dirk I.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/725,084
• Time in Patent Office: 1,012 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/300, 364/147, 364/136, 364/141
• US Class Current: 717/141
• CPC Class Codes: G05B 19/056 Programming the PLC
• CPC Class Codes: G06F 8/447 Target code generation

Abstract

An intelligent compiler particularly useful for evaluating Boolean expressions such as those associated with ladder structures. True/false paths are defined through the expressions. In a first pass for the code generation, the start code for examining each element is set out. In a second pass the relative offsets for branching from one element to the next element along both the true and false paths are filled in. In practice, execution time for evaluating ladder structures is reduced by an order of magnitude over prior techniques which use source code and an interpreter.

Claims

1. In a process where the condition of a plurality of logic elements, including a first logic element and a last logic element, controls an action, a method for preparing a computer program for determining said action, said program being for execution in a digital computer having a processor and a memory, said method comprising the steps of:

developing an expression for storage in said memory, said expression defining the effect said logic elements have on said action;

for each condition for each logic element, using said processor for examining said expression to determine another logic element within said expression which controls said action, thereby defining condition determining control paths;

generating code for execution by said computer for examining the conditions of only those logic elements necessary to determine the action in an order directed by said condition determining control paths.

2. The method defined by claim 1 wherein said action is known upon completion of said examination of each of said elements along one of said condition determining control paths.

3. The method defined by claim 1 wherein said condition determining control paths consist of a true path and a false path.

4. The method defined by claim 3 wherein said generating code step comprises the steps of:

preparing skeletal code in said memory which includes the evaluation of each of said logic elements; and

,

inserting relative offsets from said first logic element to each of said other logic elements.

5. The method defined by claim 4 including the step of simplifying said expression prior to said defining of said condition determining paths.

6. In a process where the condition of a plurality of logic elements determines the action taken by an action element, wherein said plurality of logic elements includes a last logic element, a method for preparing a computer program for determining said action to be taken by said action element, said program being for execution in a digital computer having a processor and a memory, said method comprising the steps of:

preparing an expression for storage in said memory defining the interaction between said logic elements;

for each condition of each logic element, using said processor for identifying each logic element within said expression that controls said action, thereby identifying condition determining paths within said expression;

generating code for execution by said computer for evaluating the conditions of only those logic elements necessary to determine the action, said code including instructions for branching from one of said logic elements to another along said condition determining paths.

7. The method defined by claim 6 wherein said action taken by said action element is determined by the condition of the last logic element.

8. The method defined by claim 6 wherein said expression is a Boolean expression.

9. The method defined by claim 7 or claim 8 wherein the condition for each of said logic elements is one of true and false.

10. The method defined by claim 9 including the step of simplifying said expression prior to identifying said condition determining paths.

11. In a process where the condition of a plurality of logic elements including a last logic element, controls a result, a method for preparing a computer program for determining said result, said program being for execution in a digital computer having a processor and a memory, said method comprising the steps of:

preparing a Boolean expression for storage in said memory defining the action of said elements on said result;

using said processor for preparing truth tables for each condition of each of said elements which identify each element within said expression controlling said result, thereby defining true and false paths;

generating code which upon being executed by said computer examines the condition of each of said elements and branches from one element to a next element along said true and false paths.

12. The method defined by claim 11 wherein said result is known upon said examination of the last of said elements along one of said true and false paths.

13. The method defined by claim 12 wherein said code generating step comprises:

for each of said elements, identifying said branches to said next element, along said paths;

preparing skeletal code with instructions for evaluating the conditions of each of said elements; and

inserting offsets to said elements.

14. The method defined by claim 11 or 13 including the step of simplifying said expression prior to said preparing of said truth tables.

15. In a process where the condition of a plurality of logic elements controls an action, a method for preparing a computer program for determining said action, said program being for execution in a digital computer having a processor and a memory, said method comprising the steps of:

preparing for storage in said memory a Boolean expression for said logic elements;

identifying a true path from said expression for each logic element by ignoring disjunctive elements using said processor;

identifying a false path from said expression for each logic element by ignoring conjunctive elements;

generating code which includes code which upon being executed by said computer examines the condition of each of said logic elements and branching instructions which directs branching along either said true path or false path as a function of the condition of each of of said logic elements.

16. The method defined by claim 15 including the simplification of said expression prior to said identification of said true and false paths.

17. The method defined by claim 16 wherein said simplification comprises the factoring of common terms within said expression and the removal of redundant parenthesis.

19. The method defined by claim 16 wherein said action is determined by the condition of the last one of said elements along one of said true and false paths.

20. The method defined by claims 16 or 19 including the simplification of said expressions prior to said identification of said true and false paths.

21. The method defined by claim 20 wherein said simplification comprises the factoring of common terms within said expressions and the removal of redundant parenthesis.

18. In a ladder structure comprising a plurality of rungs where each rung comprises a plurality of interconnected logic elements, the condition of said elements determining an action for said rung, a method for preparing a computer program for determining said action for each of said rungs, said program being for execution on a digital computer having a processor and memory, said method comprising the steps of:

for each of said rungs, preparing for storage in said memory a Boolean expression defining the coupling of said elements in said rung;

for each condition of each element within each expression, using said processor for determining a next element within said expression that effects said action thereby identifying true and false paths for said expression;

generating code which upon being executed by said computer is for evaluating the condition of each element in said expressions such that the order of said evaluation is dictated by said true and false paths.

22. In a ladder structure comprising a plurality of rungs where each rung includes a plurality of logic elements the conditions of which determine the rungs'"'"' output, a method for preparing a computer program for determining said outputs, said program being for execution on a digital computer having a processor and memory, said method comprising the steps of:

preparing for storage in said memory Boolean expressions for each rung which define the coupling between said elements of said rung;

using said processor for determining a true path from each of said elements in each of said expressions by ignoring disjunctive elements in said expressions;

using said processor for determining a false path from each of said elements in each of said expressions by ignoring conjunctive elements in said expressions;

generating code which upon being executed by said computer results in the evaluation of the condition of each element and which includes branching instructions which follow said true paths and false paths based on the condition of said element.

23. The method defined by claim 22 wherein said code generation step comprises:

preparation of a skeletal code in a first pass which includes instructions for the examination of each element, and a second pass wherein the paths from each element are resolved by determining relative offsets between the elements along said paths.

24. The method defined by claim 23 including the steps of optimizing said expressions prior to said determining said true and false paths.

25. The method defined by claim 24 wherein said optimization step comprises the steps of factoring common terms of disjunctive terms within said expressions and removing redundant parenthesis within said expressions.