Serial bus system and method for selection of bus subscribers
First Claim
1. A method for selection of subscribers connected to a serial bus, whereat a pair of binary logic states are actively represented on said bus, a collision signal is represented by the presence of both logic states and an idle or inactive state is represented by the concurrent lack of both logic states, with said subscribers wishing to send a message indicate this by sending a bus signal and following it by an address, whereat each of said subscribers compares said incoming address with its own address and is separated from said bus if a lack of identity is detected between the incoming address bit and its own address bit, characterized in that said bus signal preceeding said address is represented by said collision signal.
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Abstract
In a serial bus system an active representation of the logic states of a bus signal for transmission of both logic states is implemented either on two separate lines for separate transmission of the logic states thereon or on a single line with both logic states being represented by different frequencies.
In the method selection of a subscriber connected to the bus, the subscribers wishing to transmit a message indicate this by issuing a collision signal to the bus. The time period during which the collision signal is issued by each subscriber is chosen in such a way that each subscriber of the bus has the possibility to be prepared for the selection. The selection of the subscriber wishing to transmit a message then is done by means of an address comparison on a bit-by-bit basis.
100 Citations
10 Claims
- 1. A method for selection of subscribers connected to a serial bus, whereat a pair of binary logic states are actively represented on said bus, a collision signal is represented by the presence of both logic states and an idle or inactive state is represented by the concurrent lack of both logic states, with said subscribers wishing to send a message indicate this by sending a bus signal and following it by an address, whereat each of said subscribers compares said incoming address with its own address and is separated from said bus if a lack of identity is detected between the incoming address bit and its own address bit, characterized in that said bus signal preceeding said address is represented by said collision signal.
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10. A serial bus system to which a plurality of subscribers are connected with said subscribers wishing to send a message indicating this by sending a bus signal and following it by an address comprising
detecting means located at each of said subscribers for detecting a collision state represented by the concurrent presence of a pair of binary logic states, an idle or inactive state represented by a concurrent lack of both logic states, a low logic state represented by one of the pair of logic states and a high logic state represented by the other one of said pair of logic states, a bus including two transmission lines and means for producing a separate transmission of said logic states on respective ones of said lines by each of said subscribers.
Specification
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- Resources
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Current AssigneeHoneywell GmbH (Honeywell International Inc.)
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Original AssigneeHoneywell GmbH (Honeywell International Inc.)
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InventorsSchwartz, Peter U.
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Primary Examiner(s)Olms, Douglas W.
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Application NumberUS06/726,855Time in Patent Office1,014 DaysField of Search370/89, 370/85, 370/4, 370/1, 370/94, 340/825.5, 340/825.52, 375/36US Class Current370/445CPC Class CodesH04L 12/40013 Details regarding a bus con...H04L 12/4135 using bit-wise arbitration
