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Method and apparatus for the protection of D.C. motors under stalled conditions

  • US 4,725,765 A
  • Filed: 11/18/1985
  • Issued: 02/16/1988
  • Est. Priority Date: 11/18/1985
  • Status: Expired due to Term
First Claim
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1. A circuit for detecting the stalled condition of a D.C. motor comprising:

  • means for selectively applying D.C. voltage to said motor;

    means for sensing the flow of current through said D.C. motor and providing an output voltage having a level corresponding to said sensed current;

    means for establishing a first reference voltage level corresponding to a level of output voltage that is above a level corresponding to the sensed current through said D.C. motor in its normal run condition and below a level corresponding to the sensed current through said D.C. motor in its stalled condition;

    means for comparing said output voltage with said first reference voltage level and producing a stall signal whenever said output voltage is greater than said first reference voltage level;

    means for timing the occurrence of said stall signal and producing a blanking signal of a predetermined duration whenever said stall signal is continuous for a first predetermined period of time; and

    means responsive to said blanking signal for inhibiting the application of D.C. voltage to said motor for the duration of said blanking signal,wherein said timing means includes;

    means for establishing a second reference voltage level which is less than said first reference voltage level and above a level of output voltage that corresponds to the sensed current through said D.C. motor in its normal run condition;

    means for comparing said output voltage with said second reference voltage level and producing a run signal whenever said output signal is greater than said second reference signal;

    means responsive to the initial portion of said stall signal and providing a delay timing pulse having a duration equal to said first predetermined period of time;

    bistable means having a set state and a reset state respectively responsive to the end portion of said delay timing pulse and the initial portion of said run signal; and

    gating means responsive to the simultaneous occurrence of said stall signal and said bistable means in its set state for commencing the generation of said blanking signal.

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