High-speed video graphics system and method for generating solid polygons on a raster display

• US 4,725,831 A
• Filed: 04/27/1984
• Issued: 02/16/1988
• Est. Priority Date: 04/27/1984
• Status: Expired due to Fees

• Current Assignee: XTAR Corporation
• Original Assignee: XTAR Corporation
• Inventors: Coleman, Terrence J.
• Primary Examiner(s): Curtis, Marshall M.
• Application Number:
  US06/604,863
• Time in Patent Office: 1,390 Days
• Field of Search: 340/717, 340/723, 340/747, 340/750, 340/798
• US Class Current: 345/441
• CPC Class Codes: G09G 5/20 Function-generator circuits, e.g. circle generators line or curve smoothing circuits
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A real-time video graphics system for generating solid polygons on a raster display screen from X-Y vertex coordinates of the polygons. Solid objects are defined in a host processor system as three-dimensional polygons. The host processor calculates the X-Y vertex coordinates for each polygon and deposits them, along with a corresponding instruction and pixel video data, in a shared RAM. The video graphics system obtains the instruction and data from the shared RAM and calculates from the X-Y vertex coordinates the X coordinates of the left and right edges of each solid polygon for each horizontal line of the display. The system writes pixel data for a horizontal stripe of 32 pixels into a frame buffer in one frame buffer memory write cycle of approximately 320 nanoseconds. Pixel data is periodically read out of the frame buffer, one complete stripe at a time, and shifted out serially to refresh the display screen.

Claims

1. A high-speed video graphics system for generating filled polygons on a raster display screen from X-Y vertex coordinates of said polygons, said system comprising:

(a) means for receiving polygon data, said polygon data including pixel video data and the X-Y vertex coordinates for each polygon, said pixel data representing selected video attributes;

(b) calculating means for calculating from said X-Y vertex coordinates the X coordinates of the left and right edges of said polygons for each horizontal line of said display, said calculating means including

(1) subtraction means for calculating Δ

X and Δ

Y for first and second horizontally opposed segments of each polygon from the X-Y vertex coordinates for the endpoints of said first and second segments, respectively;

(2) divider means coupled to said subtraction means for calculating the slopes of said first and second segments from the respective values of Δ

X and Δ

Y;

(3) edge calculator means coupled to said divider means and responsive to said slopes of said first and second segments for calculating the left and right edge X coordinates of a first horizontal line between said first and second segments; and

(4) means for controlling said subtraction means, divider means and edge calculator means to effect parallel processing of data corresponding to said first and second horizontally opposed segments;

(c) a frame buffer having a plurality of sections each corresponding to a plurality of adjacent pixels defining a video frame portion, said frame buffer sections each including a memory location for each associated pixel;

(d) means for writing said pixel data simultaneously into the frame buffer memory locations which correspond to a selected plurality of pixels in a selected frame portion, said writing means having a control input coupled to said calculating means; and

(e) means for reading said pixel data out of said frame buffer to refresh the display screen.

2. The video graphics system of claim 1 wherein said frame portion is a horizontal stripe of pixels, said raster display has a scan rate of at least 15 frames per second, and said writing means includes means for generating a stripe address corresponding to a selected stripe.

3. The video graphics system of claim 2 wherein said frame buffer is a semiconductor memory having an address input, a data input/output coupled to all memory locations in said buffer for said selected stripe in response to a single address word supplied to said address input, and a plurality of separate write enable inputs each coupled to a respective one of said memory locations for said selected stripe;

and wherein said writing means includes means for generating write enable signals for each of said write enable inputs.

4. The video graphics system of claim 3 wherein said edge X coordinates are binary numbers each having high-order and low-order bits;

said writing means includes

(1) means coupled to said frame buffer address input for generating a stripe address in response to the high-order bits of the left edge X coordinate for said first horizontal line and for incrementing said stripe address for each successive stripe in said first horizontal line; and

(2) means for generating addresses for the left and right end pixels in an addressed stripe, said end pixel address generating means being responsive to the low-order bits of said left edge X coordinate and of the corresponding right edge X coordinate for said particular line;

and wherein said write enable signal generating means includes

(1) left and right ROMs, each ROM having n words of memory each n bits wide, each bit being associated with a predetermined write enable input and programmed in a state corresponding to a desired write enable signal, said left and right ROMs being addressed by said left and right end pixel addresses, respectively; and

(2) logic circuit means for combining the outputs of said left and right ROMs.

5. The video graphics system of claim 4 wherein said receiving means includes an instruction execution unit operative to decode and execute instructions stored in a RAM shared by said video graphics system and a host processor, said execution unit including access means for accessing said shared RAM on alternate memory cycles thereof;

and wherein said writing means is operative to write pixel data into said frame buffer for said first horizontal line while said edge calculator means operates on a subsequent horizontal line between said first and second segments.

6. The video graphics system of claim 5 wherein said stripes are at least 16 pixels wide and wherein said pixel data includes at least 4 bits per pixel.

7. The video graphics system of claim 6 wherein said receiving means and calculating means operate synchronously in response to a system clock signal;

and wherein said divider means completes a slope calculation in twelve or fewer cycles of said system clock.

8. The video graphics system of claim 1 wherein said frame buffer is a semiconductor memory having an address input, a data input/output coupled to all memory locations in said buffer for said frame portion in response to a single address word supplied to said address input, and a plurality of separate write enable inputs each coupled to a respective one of said memory locations for said frame portion;

and wherein said writing means includes means for generating write enable signals for each of said write enable inputs.

9. The video graphics system of claim 8 wherein said edge X coordinates are binary numbers each having high-order and low-order bits;

and wherein said write enable signal generating means includes ROM means for storing a plurality of enable bit patterns, each bit pattern corresponding to a desired set of write enable signals, said ROM means having an address input coupled to said calculating means.

10. The video graphics system of claim 1 wherein said receiving means includes an instruction execution unit operative to decode and execute instructions stored in a RAM shared by said video graphics system and a host processor, said execution unit including access means for accessing said shared RAM on alternate memory cycles thereof;

and wherein said writing means is operative to write pixel data into said frame buffer for said first horizontal line while said edge calculator means operates on a subsequent horizontal line between said first and second segments.

12. The video graphics system of claim 1 wherein said receiving means and calculating means operate synchronously in response to a system clock signal;

and wherein said divider means completes a slope calculation in twelve or fewer cycles of said system clock.

11. The video graphics system of claim wherein said frame portion is a horizontal stripe of at least 16 pixels and wherein said pixel data includes at least 4 bits per pixel.

13. A method of generating filled polygons on a raster display screen from X-Y vertex coordinates of said polygons, said method comprising the steps:

(a) receiving polygon data including the X-Y vertex coordinates of a particular polygon and pixel video data representing selected video attributes for said particular polygon;

(b) calculating from said X-Y vertex coordinates the X coordinates of the left and right edges of said particular polygon for each horizontal line of said display, said calculating step including

(1) calculating Δ

X and Δ

Y for first and second horizontally opposed segments of said particular polygon from the X-Y vertex coordinates for the endpoints of said first and second segments, respectively;

(2) calculating the slopes of said first and second segments from the respective values of Δ

X and Δ

Y; and

(3) calculating from said slopes of said first and second segments the left and right edge X coordinates of a first horizontal line between said first and second segments;

wherein the operations defining said calculating step are controlled to effect parallel processing of data corresponding to said first and second horizontally opposed segments;

(c) writing said pixel data simultaneously into a frame buffer in memory locations which correspond to a selected plurality of pixels in a selected video frame portion; and

(d) reading said pixel data out of said frame buffer to refresh the display screen.

14. The method of claim 13 wherein said writing step is performed for said first horizontal line while the edge X coordinates are calculated for a subsequent horizontal line between said first and second segments.

15. A high-speed video graphics system for generating filled polygons on a raster display screen from X-Y vertex coordinates of said polygons, said system comprising:

(a) means for receiving polygon data, said polygon data including pixel video data and the X-Y vertex coordinates for each polygon, said pixel data representing selected video attributes;

(b) calculating means for calculating from said X-Y vertex coordinates the X coordinates of the left and right edges of said polygons for each horizontal line of said display, said calculating means including

(1) subtraction means for calculating Δ

X and Δ

Y for first and second horizontally opposed segments of each polygon from the X-Y vertex coordinates for the endpoints of said first and second segments, respectively;

(2) divider means coupled to said subtraction means for calculating the slopes of said first and second segments from the respective values of Δ

X and Δ

Y;

(3) edge calculator means coupled to said divider means and responsive to said slopes of said first and second segments for calculating the left and right edge X coordinates of a first horizontal line between said first and second segments; and

(4) means for controlling said subtraction means, divider means and edge calculator means to effect parallel processing of data corresponding to said first and second horizontally opposed segments;

(c) a frame buffer having a plurality of sections each corresponding to a plurality of adjacent pixels defining a video frame portion, said frame buffer sections each including a memory location for each associated pixel;

(d) means for writing said pixel data simultaneously into all frame buffer memory locations, in a selected frame buffer section, which correspond to pixels between said left and right edge X coordinates of said first horizontal line; and

(e) means for reading said pixel data out of said frame buffer to refresh the display screen.

16. The video graphics system of claim 15 wherein said frame portion is a horizontal stripe of at least 16 adjacent pixels and wherein said pixel data includes at least 4 bits per pixel.