Method of fabricating semiconductor device

• US 4,727,038 A
• Filed: 08/22/1985
• Issued: 02/23/1988
• Est. Priority Date: 08/22/1984
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kamoto, Satoru, Watabe, Kiyoto
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Thomas, Tom
• Application Number:
  US06/768,374
• Time in Patent Office: 915 Days
• Field of Search: 29/571, 29/576 B, 29/578, 29/577 C, 148/1.5, 148/106, 148/147, 357/23.3, 156/643
• US Class Current: 438/304
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence
• CPC Class Codes: Y10S 148/106 Masks, special

Abstract

A method of fabricating a MOS field effect semiconductor device having an LDD structure is described in which an insulating film is formed on a gate electrode and a layer of polycrystalline silicon, oxide, high melting point metal or a silicide of a high melting point metal is formed on a wafer and etched away by unisotropic RIE, except a portion thereof on a sidewall of the gate. With the resulting structure, degradation of the transconductance of the device due to injection of hot carriers is prevented. Also, the size of the device can be minimized without unduly increasing the resistances of the drain/source region, the gate electrode, and the contacts of the device.

Claims

1. A method of fabricating a semiconductor device comprising the steps of:

forming, on a silicon substrate (1) having a first conductivity type, a gate electrode layer (50) comprising a gate insulating film (2) and a gate electrode (3),

forming a low impurity concentration portion (4) of a source/drain region by injecting an impurity of a second conductivity type into a surface portion of said silicon substrate while using said gate electrode layer as a mask,

forming, on an exposed surface portion of said silicon substrate and on said gate electrode, a layer of a high melting point metal (51) or a silicide of a high melting point metal,

anisotropically etching said layer of said high melting point metal or silicide of a high melting point metal to leave a gate sidewall portion (52) of said layer of said high melting point metal or silicide of a high melting point metal on a sidewall portion of said gate electrode layer,

removing said gate insulating film, except a portion thereof beneath said gate electrode, and

forming a high impurity concentration portion (5) of said source/drain region by injecting an impurity of said second conductivity type while using said gate electrode layer and said gate sidewall portion as a mask.

2. A method of fabricating a semiconductor device comprising the steps of:

forming, on a silicon substrate having a first conductivity type, a gate electrode comprising a gate insulating film and a polycrystalline silicon layer,

forming a low concentration source/drain region by injecting impurity ions, having a second, different, conductivity type from that of said substrate, into a surface portion of said substrate, while using said electrode as a mask,

siliciding a desired region of said electrode or said electrode and said source/drain region and forming a high impurity concentration portion of said source/drain region by injecting an impurity of said second type while using said gate electrode and at least a portion of said desired region as a mask,

forming an insulating film on said substrate,

forming contact holes in said high concentration region of said source/drain, and

connecting wiring through said contact holes.

3. The method as claimed in claim 2, wherein said step of siliciding comprises the steps of:

forming a high melting point metal layer on said silicon substrate,

siliciding said gate electrode by heat treatment of said high melting point metal layer, and removing a portion of said high melting point metal layer which is not silicided.

4. The method as claimed in claim 2, wherein said siliciding step comprises the steps of:

forming a resist film on said silicon substrate,

removing a portion of said gate insulating film on a desired region of said source/drain while using said resist film as a mask,

removing said resist film,

forming a high melting point metal layer on said substrate,

siliciding portions of said high melting point metal layer around said gate electrode and said source drain region, and

removing portions of said high melting point metal layer which are not silicided, and heat-treating said silicon substrate.

5. The method as claimed in claim 4, wherein said siliciding step comprises, between said selective removal step of said gate insulating film and said resist film removal step, the step of injecting ions having a different conductivity type from that of said substrate into a desired region of said source/drain region while using said resist film as a mask.

6. The method as claimed in claim 2, wherein said siliciding step comprises the steps of:

forming a resist film on said silicon substrate,

removing a portion of said gate insulating film on a desired region of said source/drain region while using said resist film as a mask,

removing said resist film,

selectively forming on an exposed silicon surface of layer of a high melting point metal or a silicide of a high melting point metal using LPCVD, and

heat treating said silicon substrate.

7. A method of fabricating a semiconductor device comprising the steps of:

forming, on a silicon substrate having a first conductivity type, a gate electrode layer comprising a gate insulating film and a gate electrode, said gate electrode being formed with a surface for contacting a portion of a corresponding surface of said gate insulating film such that the remaining portion of said corresponding surface is an exposed portion thereof,

forming a low impurity concentration portion of a source/drain region by injecting an impurity of a second conductivity type into a surface portion of said silicon substrate while using said gate electrode as a mask.

forming, on said exposed portion of said corresponding surface of said gate insulating film and on said gate electrode, a layer of a high melting point metal or a silicide of a high melting point metal,

anisotropically etching said layer of said high melting point metal or silicide of a high melting point metal to leave a gate sidewall portion of said layer of said high melting point metal or silicide of a high melting point metal on a sidewall portion of said gate electrode layer and contacting said exposed portion of said corresponding surface,

removing said gate insulating film, except a portion thereof beneath said gate electrode and said gate sidewall portion, and

forming a high impurity concentration portion of said source/drain region by injecting an impurity of said second conductivity type while using said gate electrode and said gate sidewall portion as a mask.