Staging memory for massively parallel processor

• US 4,727,474 A
• Filed: 02/18/1983
• Issued: 02/23/1988
• Est. Priority Date: 02/18/1983
• Status: Expired due to Fees

• Current Assignee: Loral Corporation (Newell Brands Inc.)
• Original Assignee: Loral Corporation (Newell Brands Inc.)
• Inventors: Batcher, Kenneth E.
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Munteanu, Florin
• Application Number:
  US06/468,028
• Time in Patent Office: 1,831 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/514, 364/516, 364/518, 358/10, 358/11, 358/12, 340/750, 340/799, 340/801, 382/44-46
• US Class Current: 712/14
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

The invention herein relates to a computer organization capable of rapidly processing extremely large volumes of data. A staging memory is provided having a main stager portion consisting of a large number of memory banks which are accessed in parallel to receive, store, and transfer data words simultaneous with each other. Substager portions interconnect with the main stager portion to match input and output data formats with the data format of the main stager portion. An address generator is coded for accessing the data banks for receiving or transferring the appropriate words. Input and output permutation networks arrange the lineal order of data into and out of the memory banks.

Claims

1. A computer organization, comprising:

a host computer;

a program and data management unit;

a processing array unit;

an array control unit interconnected among said host computer, program and data management unit, and processing array unit; and

a staging memory interconnected between said host computer, program and data management unit, and processing array unit, said staging memory comprising;

input means connected to said host computer, program and data management unit, and said processing array unit for receiving data therefrom;

output means connected to said host computer, program and data management unit, and said processing array unit for passing data thereto; and

a main stager interposed between said input and output means for receiving and maintaining large volumes of data therein, said main stager including a plurality of memory banks for receiving and maintaining data, said banks receiving and transferring data in parallel, said memory banks being connected in parallel to addressing means for accessing storage locations in said memory banks and wherein a memory bank L stores words whose addresses are congruent to L modulo the number of memory banks.

2. The computer organization according to claim 1 wherein said plurality of memory banks is a number evenly divisible by four.

3. The computer organization according to claim 1 wherein said addressing means includes a code generating means for mutually exclusively accessing a word in each of said memory banks.

4. The computer organization according to claim 3 wherein said main stager further includes an input permutation network and an output permutation network respectively connected to said input and said output means, said input permutation network routing input data words to the memory banks containing a corresponding word address, and said output permutation network routing output data words from said memory banks to said output means.

5. The computer organization according to claim 4 wherein said input means includes an input port for shuffling input data prior to passage of said data to said input permutation network.

6. The computer organization according to claim 5 wherein said output means includes an output port for shuffling output data prior to passage of said data to said output permutation network.