Logically transportable microprocessor interface control unit permitting bus transfers with different but compatible other microprocessors

• US 4,727,477 A
• Filed: 03/22/1985
• Issued: 02/23/1988
• Est. Priority Date: 03/22/1985
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gavril, Bruce D.
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Chan, Emily Y.
• Application Number:
  US06/714,761
• Time in Patent Office: 1,068 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/64
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A transportable bus control architecture for single-chip microprocessors consists of an interface control unit that is logically independent of the associated co-resident, common clock-driven microprocessing unit. This independence allows the interface control unit logic to be used with a variety of microprocessing units. The interface control unit presents an external appearance that is compatible with the peripheral devices of a specific microprocessor referred to as the "compatible microprocessor", thereby making available to an associated co-resident microprocessing unit the support devices of the compatible microprocessor. The interface control unit can also access other external devices not related and transparent to the devices of the compatible microprocessor. The interface control unit is logically divided into an execution section and a control section. The execution section is controlled by the control section and comprises various registers, latches, multiplexers, logic, and data and address paths that provide communication between the co-resident microprocessing unit and off-chip devices. The control section of the interface control unit executes commands from the co-resident microprocessing unit and also performs bus arbitration, interrupt, and external reset functions. Bus cycles are memory-access or service, depending on the command from the co-resident microprocessing unit. Service cycles perform the interrupt acknowledge functions and other sense and control functions requested by the co-resident microprocessing unit. These sense and control functions have the special feature of being pin-programmable and pin-readable by the microprocessing unit. All action initiated by commands from the microprocessing unit elicits a comprehensive status response from the interface control unit.

Claims

1. A single-chip microprocessor comprising:

external signal pins to which off-chip devices are connected;

a microprocessing unit; and

an interface control unit, said interface control unit being connected to said microprocessing unit and to said external signal pins of said single-chip microprocessor, said microprocessing unit and said interface control unit being logically distinct elements, such that said interface control unit is logically transportable for use with other and different microprocessing units;

said interface control unit comprising;

execution means connected to said microprocessing unit and to said external signal pins; and

control means for controlling said execution means and for performing signal sequencing at said external signal pins, said signal sequencing being called a bus cycle, said control means being responsive to commands from said microprocessing unit and to control signals from said off-chip devices;

said control means including command means responsive to said commands from said microprocessing unit and status means for presenting status to said microprocessing unit describing the outcome of each command, wherein said command means causes said execution means to perform a data transfer in response to a command from said microprocessing unit, and said status means presents the outcome status of said particular command upon logical completion of said data transfer.

2. The single-chip microprocessor as recited in claim 1 wherein said execution means and said control means are designed to provide an external appearance at said external signal pins that is compatible with peripheral devices of a specific microprocessor called the compatible microprocessor, thereby enabling at least one peripheral device of said compatible microprocessor to be attached to said single-chip microprocessor and to communicate with said co-resident microprocessing unit.

3. The single-chip microprocessor recited in claim 2 wherein said execution means and control means further include extended means for attaching and operating other peripheral devices of different type than associated with said compatible microprocessor, said extended means and its operation being transparent to any co-attached device of said compatible microprocessor.

4. The single-chip microprocessor recited in claim 3 wherein said extended means comprises:

means for generating non-compatible signals not physically detectable by any attached device of said compatible microprocessor; and

means for generating compatible signals physically detectable by, but logically transparent to, all attached devices of said compatible microprocessor, said compatible signals conforming to the natural communication protocol of the devices of said compatible microprocessor, said other peripheral devices of different type than associated with said compatible microprocessor using said non-compatible signals and said compatible signals in the process of communicating with said interface control unit.

5. The single-chip microprocessor recited in claim 3 wherein said control means includes mixed-width device handling means for dynamically controlling said execution means in response to an addressed off-chip device'"'"'s width-identifying response to a bus cycle.

6. The single-chip microprocessor recited in claim 3 wherein said control means includes accessing means for accessing operands from said off-chip devices at any byte location including those locations which do not correspond to an integral boundary of the accessed operand.

7. The single-chip microprocessor recited in claim 3 wherein said control means is responsive to an external control signal for varying the minimum duration of a bus cycle.

8. The single-chip microprocessor recited in claim 1 wherein said control means further comprises:

initiation sequence means for generating initiation signals identifying said bus cycle to at least one off-chip device;

detection sequence means for responding to the external signals produced by said off-chip device in response to said initiation signals; and

termination sequence means for concluding said bus cycle.

9. The single-chip microprocessor recited in claim 3 wherein said bus cycle comprises outbound control signals which are specified explicitly by said command from said co-resident microprocessing unit.

10. The single-chip microprocessor recited in claim 9 wherein said external signals produced by said off-chip device are in response to said bus cycle, said external signals being identified explicitly in said status describing said outcome of said command.

11. The single-chip microprocessor recited in claim 1 wherein said control means further comprises:

bus arbitration means for granting temporary and exclusive use to an off-chip master device of any bus derived from said external pins of said single-chip microprocessor, said arbitration means being logically independent of said control means responsive to said commands from said co-resident microprocessing unit, and said granting being subject to enablement by said control means as a condition for being exhibited to said off-chip master device; and

12. bus grant enable means responsive to said bus arbitration means for enabling and disabling said granting of said bus.

14. The bus control architecture recited in claim 12 wherein said interface control unit further comprises status means connected to said control means for buffering and transmitting sataus response signals from said interface control unit to said microprocessing unit according to the outcome of the execution of commands from said associated microprocessing unit.

16. The bus control architecture recited in claim 14 wherein said microprocessing unit may access operands which are not aligned with integral boundaries of said externally connected support devices, and said control means further including alignment detection means for accessing non-aligned operands piecewise using separate bus cycles at each addressed field in memory address space within which any portion of the non-aligned operand is contained or directed.

13. A bus control architecture for microprocessors consisting of a logically independent interface control unit capable of being used with a variety of microprocessing units, said interface control unit permitting a microprocessing unit to be used with externally connected support devices of another, different microprocessor, said interface control unit being connected to memory means for storing data, said memory means being divided into memory address space and service address space, said interface control unit comprising:

address means for providing an output address unit and said externally connected support devices during a bus cycle;

data means for providing a bidirectional data path between said microprocessing unit and said externally connected support devices during a bus cycle;

processor command means for receiving and buffering commands from said microprocessing unit to said interface control unit; and

control means connected to said processor command means and responsive to commands from said microprocessing unit for performing either a memory access bus cycle or a service access bus cycle depending on the command from said microprocessing unit wherein memory address space is accessed during a memory access bus cycle and service cycle address space is addressed during a service bus cycle, said service bus cycle address space being divided into interrupt-acknowledge address space for space externally connected support devices and control and sense address space of said microprocessing unit to permit an extension of the functional capability of said microprocessing unit in a manner that is transparent to said externally connected support devices of said compatible microprocessor.

15. The bus control architecture recited in claim 13 wherein said externally connected support devices of said compatible microprocessor may have various and different address and data widths, said externally connected support devices providing a width-identifying response to a bus cycle, and said control means further including mixed-width means responsive to a width-identifying response for dynamically initiating the required number of bus cycles to fulfill an access command from said microprocessing unit.

17. The bus control architecture as recited in claim 13 wherein said control means further includes macrocycle control means for logically chaining related bus cycles for serialized access of said externally connected support devices in a macrocycle, said macrocycle control means prohibiting interruption of a macrocycle by any one of said externally connected support devices until said macrocycle has been completed.

18. The bus control architecture recited in claim 13 wherein said control means is further connected and responsive to other externally connected devices unrelated to said compatible microprocessor, the communication between said control means and said other externally connected devices being transparent to the connected support devices of said compatible microprocessor.

19. The bus control architecture recited in claim 17 wherein said control means further includes rerun means responsive to said externally connected support devices and said other externally connected devices for distinguishing between bus cycle rerun requests of said externally connected support devices and said other externally connected devices with means for the latter type of device to cancel a rerun request, said control means reporting a cancellation of a rerun requenst to said microprocessing unit.

20. The bus control architecture as recited in claim 13 wherein said control means further includes cancellation detection means responsive to a cancellation signal from an externally connected support device for cancelling that device'"'"'s earlier response to a bus cycle, thereby providing for the overlap of that device'"'"'s operation with the operation of said interface control unit.

21. The bus control architecture recited in claim 13 wherein said control means further includes interrupt detection means for detecting and reporting via said status means interrupt signals from said externally connected support devices.

22. The bus control architecture recited in claim 20 wherein said interrupt detection means includes means for detecting and reporting via said status means interrupt signals from other externally connected devices which are unrelated to said compatible microprocessor.

23. The bus control architecture recited in claim 21 wherein said interface control unit further includes bus arbitration means connected to said control means for effecting an orderly, prioritized and dynamic sharing of said address means and said data means.

24. The bus control architecture recited in claim 13 wherein said control means of said interface control unit unconditionally reports all externally connected device responses to said microprocessing unit via said status means during service bus cycles, said associated microprocessing unit controlling the content of the paths of said address means and said data means during said service bus cycles.