Method and apparatus for isolating faults in a digital logic circuit

• US 4,727,545 A
• Filed: 09/02/1986
• Issued: 02/23/1988
• Est. Priority Date: 09/02/1986
• Status: Expired due to Fees

• Current Assignee: Digital Equipment Corporation (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Petty, Robert C., Glackemeyer, Richard E., Page, Calvin F.
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/902,614
• Time in Patent Office: 539 Days
• Field of Search: 371/23, 371/25, 371/27, 364/200, 364/906, 364/578, 324/73 R, 324/73 M, 324/73 PC
• US Class Current: 714/33
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G06F 11/2273 Test methods
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

The method and apparatus for isolating faults in circuitry of a digital computer includes the use of a fault isolation generation program which provides a data base containing a list of possible faulty components for each cycle of the computer'"'"'s clock for execution by a service processor of the actual computer during testing. The fault isolation generation program is generated by using a simulator loaded with a mathematical model of the actual computer in connection with the execution of the diagnostic program executed on the actual computer during testing. The fault isolation program generates a list of circuit elements capable of generating fault indications, excluding circuit elements not capable of generating such fault indications.

Claims

1. A method of generating a list of circuit elements for use in isolating faults in a logic circuit, the logic circuit having a plurality of circuit elements and a plurality of test points at the outputs of predetermined ones of the circuit elements, the circuit elements interconnected in successive stages to form a plurality of signal paths extending upstream from the test points, the logic circuit performing operations in accordance with a plurality of successive clock cycles, the method comprising the steps of:

(a) simulating the execution of a diagnostic procedure on the logic circuit to perform a predetermined operation of the logic circuit using a logic model including simulated circuit elements and simulated test points corresponding to the logic circuit elements and logic circuit test points;

(b) storing the logic states of the simulated test points at a plurality of clock cycles during the simulated execution of the diagnostic procedure;

(c) specifying subsets of the stored logic states as seed signals at which a malfunction of the predetermined operation can be detected;

(e) examining the simulated circuit elements generating each seed signal to identify signal paths being supplied as inputs to the examined simulated circuit elements;

(f) evaluating the simulated circuit elements generating the seed signals based on predetermined criteria to eliminate signal paths and simulated circuit elements thereof which are incapable of causing the malfunction indicated by the seed signals;

(g) recursively evaluating the simulated circuit elements of successive upstream stages of non-eliminated signal paths and simulated circuit elements thereof according to the predetermined criteria; and

(h) storing the non-eliminated circuit elements as candidates capable of causing the malfunctions.

2. The method according to claim 1, further comprising the step of determining if a circuit element is eliminated based on a predetermined assumed signal set.

3. The method according to claim 1, wherein the evaluating step is performed for each one of the clock cycles and comprises the sub-steps of:

(a) determining if a circuit element is a clocked or a non-clocked circuit element;

(b) storing the logic states of each clocked circuit element for processing at a different one of said clock cycles;

(c) storing the logic states of the outputs of each non-clocked circuit element;

(d) changing the logic state of each input of each non-clocked circuit element separately to determine if the change in input logic state affects the output logic state;

(e) eliminating signal paths upstream of each input when a change in logic state of the input does not affect the output logic state; and

(f) restoring a changed input logic state before changing the logic state of another input.

4. The method according to claim 1, wherein the simulating step comprises the sub-steps of:

(a) loading a simulation program into a host computer; and

(b) executing the simulation program on the host computer in conjunction with a hardware accelerator.

5. The method according to claim 1, wherein the specifying step includes specifying visible signal names and specific clock cycles at which the logic states of the visible signals are indicative of normal or abnormal operation of the logic circuit.

6. A method for isolating faults in a logic circuit having a plurality of circuit elements interconnected in successive stages to form a plurality of signal paths and a plurality of test points at the outputs of predetermined ones of the circuit elements, and executing instructions in accordance with the successive clock cycles, the method comprising the steps of:

(a) executing a diagnostic procedure on the logic circuit to detect faulty operation of the logic circuit;

(b) storing a list of circuit elements capable of generating a fault indication at predetermined ones of the test points activated by the diagnostic procedure at predetermined ones of the clock cycles and excluding circuit elements not capable of causing such fault indications;

(c) executing a fault isolation procedure to examine the logic states of the predetermined test points;

(d) comparing the examined logic states to the logic states of the predetermined test points during normal operation of the logic circuit; and

(e) outputting a list of circuit elements contained in the fault isolation procedure which correspond to the logic states identified by the comparison step.

7. The method according to claim 6, wherein the step of executing the fault isolation procedure includes performing the execution on an auxiliary service processor interfaced with the logic circuit.