Watchdog activity monitor (WAM) for use wth high coverage processor self-test

• US 4,727,549 A
• Filed: 09/13/1985
• Issued: 02/23/1988
• Est. Priority Date: 09/13/1985
• Status: Expired due to Fees

• Current Assignee: United Technologies Corporation (Rtx Corporation)
• Original Assignee: United Technologies Corporation (Rtx Corporation)
• Inventors: Versailles, Richard E., Crosset, Richard W. III, Tulpule, Bhalchandra R.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/758,251
• Time in Patent Office: 893 Days
• Field of Search: 371/15, 371/25, 371/62, 324/73 R, 324/73 AT, 324/73 PC
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A high fault coverage, instruction modeled self-test for a signal processor in a user environment is disclosed. The self-test executes a sequence of sub-tests and issues a state transition signal upon the execution of each sub-test. The self-test may be combined with a watchdog activity monitor (WAM) which provides a test-failure signal in the presence of a counted number of state transitions not agreeing with an expected number. An independent measure of time may be provided in the WAM to increase fault coverage by checking the processor'"'"'s clock. Additionally, redundant processor systems are protected from inadvertent unsevering of a severed processor using a unique unsever arming technique and apparatus.

Claims

1. A watchdog activity monitor (WAM) responsive to a power-on-reset signal for providing a start-up sever signal for severing selected signal processor output signals and responsive to a subsequent unsever request signal for providing an unsever signal for unsevering the selected processor output signals, the WAM for use with a signal processor repetitive self-test, the self-test having associated therewith a start signal pulse indicative of the beginning of each self-test, state transition signal pulses provided by the processor during each self-test upon the occurrence of test state transitions, and a reset signal pulse provided by the processor indicative of the conclusion of each self-test, the WAM comprising:

counter means, responsive during each repetition of the self-test to the start signal pulse from the signal processor and the state transition signal pulses for providing an output signal having a magnitude indicative of the number of state transition signal pulses received after the reception of the start signal pulse; and

sever logic means, responsive to the reset signal pulse and to said output signal for providing a sever signal for severing the selected signal processor output signals if the magnitude of said output signals is different from a selected magnitude at the time the reset signal pulse is provided.

2. The WAM of claim 1, further comprising:

independent timing means responsive to selected processor pulses for timing the interval between said selected processor pulses and providing a timing signal indicative of the duration of said interval; and

means for comparing the magnitude of said timing signal to a selected magnitude and for providing a sever signal for severing the selected signal processor output signals if said timing signal magnitude differs from said selected magnitude.

3. The WAM of claim 1, further comprising further sever logic means, responsive to a first to occur unsever request signal for providing an unsever signal for unsevering the selected output signals of the signal processor and responsive to any subsequent unsever request signals for providing a sever signal for severing the selected output signals of the signal processor.

4. The WAM of claim 1, further comprising further sever logic means responsive to a power-on-reset signal for providing the start-up sever signal for severing the signal processor output on start-up and responsive to the first to occur of any subsequent unsever request signals for providing an unsever signal for unsevering the selected output signals of the signal processor and responsive to any additional unsever request signals for providing a sever signal for severing the selected output signals of the signal processor.

5. A watchdog activity monitor (WAM), responsive to an unsever request signal by providing an unsever signal for unsevering selected output signals of a signal processor, the WAM for use with a signal processor repetitive self-test having associated therewith a number of sub-tests, a clock signal, a repetitive frame synchronizing signal pulse and a self-test window signal for indicating a subframe within each repetitive frame within which subframe a self-test may be executed, a start signal pulse and a reset signal pulse, occurring respectively, at the beginning and end of each self-test, and the processor providing, during the course of each self-test, state transition signal pulses upon the occurrence of transitions between selected sub-test states, the WAM comprising:

logic means, responsive to the frame synchronizing pulses and the window signals for enabling a self-test sequence within each subframe, said logic means also responsive, during each subframe, to a start signal pulse from the signal processor for providing a load count signal and a count enable signal in response thereto, siad logic means also responsive, during each subframe to a reset signal pulse from the signal processor for providing a reset request signal in response thereto;

counter means, responsive to said load count signal and to said count enable signal, for respectively loading a count signal magnitude and for enabling the counting of a plurality of state transition signal pulses during each subframe, said counter means also responsive to the state transition signal pulses and the clock signal from the processor for counting upon each simultaneous reception of both a clock signal pulse and an edge of the state transition pulse within a subframe, said counter means providing a counted output signal having a magnitude indicative of the number of state transition signals received during the subframe; and

means responsive to said reset request signal and to said counted output signal for comparing, at the time said reset request signal is received, the magnitude of said counted output signal to a reference signal having a magnitude indicative of the magnitude of the number of selected sub-test states and for providing a sever signal for severing the selected output signals of the signal processor if said counted output signal magnitude differs from said reference signal magnitude.

6. The WAM of claim 5, wherein said logic means further comprises means for comparing the sequence of received window, start, and reset signals within each repetitive frame to a selected expected sequence and for providing a sever request signal in the presence of a received signal sequence different from the selected expected sequence.

7. The WAM of claim 5, further comprising:

independent timing means, responsive to selected signal pulses from the processor for measuring a time interval between said selected processor signal pulses and providing an interval signal indicative of the duration of said interval; and

means for comparing the magnitude of said interval signal to a time reference signal having a magnitude indicative of the duration of each frame and for providing a sever signal for severing the selected signal processor output signals in the presence of said interval signal magnitude differing from said time reference signal magnitude.

8. The WAM of claim 5, further comprising;

sever logic means, responsive to a first to occur unsever request signal for providing an unsever signal for unsevering the selected output signals of the signal processor and responsive to any subsequent unsever signals for providing a sever signal for severing the selected output signals of the signal processor.

9. The WAM of claim 5, further comprising:

sever logic means responsive to a power-on-reset signal for providing a sever signal for severing the selected signal processor output signals on start-up and responsive to the first to occur of any subsequent unsever request signals for providing an unsever signal for unsevering the selected output signals of the signal processor and responsive to any additional unsever request signals occurring after said first to occur unsever request signal for providing a sever signal for severing the selected signal processor output signals.

10. A method of repetitively testing a signal processor which has selected output signals unsevered after start-up in response to an unsever request signal, each test repetition having a start signal associated with the commencement thereof, state transition signals indicative of transitions therein and a reset signal associated with the conclusion thereof, comprising the steps of:

providing, for each test repetition, a start signal from the signal processor for indicating the starting of a sequence of a number of processor sub-tests;

sequentially executing, for each test repetition, a selected number of processor subtests, the processor providing a transition signal indicative of subtest states;

the signal processor providing, for each test repetition, a reset signal indicative of the conclusion of the last of the selected number of subtests;

providing, for each test repetition, in response to said transition signals a count signal having a magnitude indicative of the number of transition signals provided for comparing said count signal magnitude, in response to said reset signal, to a reference signal having a magnitude indicative of said selected number of sub-tests; and

providing, for each test reptiition, a sever signal for severing the selected processor output signals in the presence of said count signal magnitude differing from said reference signal magnitude.

11. The method of claim 10, further comprising the steps of:

providing an independent clock signal for providing an independent measure of time;

using said independent clock signal to measure the elapsed time between successive selected signal processor signals occurring within corresponding successive test repetition periods and providing an elapsed time signal having a magnitude indicative of the duration thereof;

comparing the magnitude of said elapsed time signal to a selected signal magnitude indicative of the processor clock period; and

providing a sever signal for severing the selected processor output signals in the presence of said elapsed time signal magnitude differing from said selected signal magnitude.

12. The method of claim 10, further comprising the steps of severing the selected output signals of the signal porcessor in the presence of said sever signal.

13. The method of claim 10, further comprising the steps of:

unsevering the selected output signals of the signal processor after start-up in response to a first to occur unsever request signal; and

providing a sever signal for severing the selected output signals of the signal processor in response to any unsever request signals occurring subsequent to said first to occur unsever request signal.