Charge-coupled device with reduced signal distortion

• US 4,727,560 A
• Filed: 04/25/1986
• Issued: 02/23/1988
• Est. Priority Date: 05/30/1985
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Veendrick, Hendrikus J. M., Pfennings, Leonardus C. M. G., Van Zanten, Adrianus T.
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US06/855,652
• Time in Patent Office: 669 Days
• Field of Search: 357/24, 377/57-63
• US Class Current: 377/60
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H01L 29/76808 Input structures

Abstract

The invention relates to a CCD input and reference charge generator, in which the occurrence of electron injection into the substrate (due to cross-talk to the substrate) and hence undesired signal distortions is prevented. For this purpose, the generator is provided with a voltage divider (26) which is constituted at least for a part (28) by a resistance element arranged outside the substrate, for example, by a polycrystalline silicon resistor. Thus, it is achieved that input diode zones (11) are no longer connected to the substrate voltage.

Claims

1. A charge-coupled device comprising a monocrystalline semiconductor body having a layer-shaped region of the one conductivity type which adjoins a major surface and is provided with:

a charge transport channel for storing and transporting supplied information in the form of charge packets;

electrical connection means for applying a voltage V_BB to the layer-shaped region;

an input circuit comprising a zone (designated as an input diode) of the second conductivity type, and supply means for supplying a signal-dependent voltage to the input diode, characterized in that the said supply means comprise a voltage divider having a junction point which is coupled to the input diode and a first resistance element connected between the junction point and a reference voltage and a second resistance element connected between the junction point and V_BB, which second resistance element comprises an element arranged outside the monocrystalline semiconductor body, and the second resistance element comprises a resistance layer which is applied to an insulating layer covering the surface of the semiconductor body.

2. A charge-coupled device as claimed in claim 1, characterized in that there is present above the charge transport channel a row of clock electrodes, which, viewed in the charge transport direction, each comprise a transfer part and a storage part arranged consecutively, internal means being provided by means of which, when the same voltage is applied to both parts, a potential barrier for the charge carriers to be transported is induced under the transfer part and a potential well is induced under the storage part.

3. A charge-coupled device as claimed in claim 2, characterized in that the first resistance element is also formed by a resistance layer deposited on the insulating layer.

4. A charge-coupled device as claimed in claim 3, characterized in that the resistance layer comprises a layer of polycrystalline silicon.

5. A charge-coupled device as claimed in claim 2, characterized in that the resistance layer comprises a layer of polycrystalline silicon.

6. A charge-coupled device as claimed in claim 2, characterized in that the reference voltage is a voltage V_SS, for example earth potential, for which it holds that |V_SS |<

|V_BB |.

7. A charge-coupled device as claimed in claim 2, characterized in that there is connected between the said reference voltage and the said junction point (designated hereinafter as the first junction point) of the said voltage divider (designated hereinafter as the first voltage divider) a second voltage divider comprising a third resistance element connected between the reference voltage and a second junction point and a fourth resistance element connected between the second junction point and the first junction point, and in that switching means are present, by means of which the input diode is connected, depending upon the input signal, to the first or the second junction point.

8. A charge-coupled device as claimed in claim 7, characterized in that the said switching means comprise two insulated gate field effect transistors, one of which is connected between the first junction point and the input diode and the other of which is connected between the second junction point and the input diode, and in that further means are provided, by means of which the input signal can be supplied to the gate electrode of one field effect transistor and the inverted input signal can be supplied to the gate electrode of the other field effect transistor.

9. A charge-coupled device as claimed in claim 7, characterized in that the third and the fourth resistance elements each comprise an insulated gate field effect transistor.

10. A charge-coupled device as claimed in claim 9, characterized in that the said switching means comprise two insulated gate field effect transistors, one of which is connected between the first junction point and the input diode and the other of which is connected between the second junction point and the input diode, and in that further means are provided, by means of which the input signal can be supplied to the gate electrode of one field effect transistor and the inverted input signal can be supplied to the gate electrode of the other field effect transistor.

11. A charge-coupled device as claimed in claim 1, characterized in that the first resistance element is also formed by a resistance layer deposited on the insulating layer.

12. A charge-coupled device as claimed in claim 11, characterized in that the resistance layer comprises a layer of polycrystalline silicon.

13. A charge-coupled device as claimed in claim 1, characterized in that the resistance layer comprises a layer of polycrystalline silicon.

14. A charge-coupled device as claimed in claim 1, characterized in that the reference voltage is a voltage V_SS, for example earth potential, for which it holds that |V_SS |<

|V_BB |.

15. A charge-coupled device as claimed in claim 1, characterized in that there is connected between the said reference voltage and the said junction point (designated hereinafter as the first junction point) of the said voltage divider (designated hereinafter as the first voltage divider) a second voltage divider comprising a third resistance element connected brtween the reference voltage and a second junction point and a fourth resistance element connected between the second junction point and the first junction point, and in that switching means are present, by means of which the input diode is connected, depending upon the input signal, to the first or the second junction point.

16. A charge-coupled device as claimed in claim 15, characterized in that the said switching means comprise two insulated gate field effect transistors, one of which is connected between the first junction point and the input diode and the other of which is connected between the second junction point and the input diode, and in that further means are provided, by means of which the input signal can be supplied to the gate electrode of one field effect transistor and the inverted input signal can be supplied to the gate electrode of the other field effect transistor.

17. A charge-coupled device as claimed in claim 15, characterized in that the third and the fourth resistance elements each comprise an insulated gate field effect transistor.

18. A charge-coupled device as claimed in claim 17, characterized in that the said switching means comprise two insulated gate field effect transistors, one of which is connected between the first junction point and the input diode and the other of which is connected between the second junction point and the input diode, and in that further means are provided, by means of which the input signal can be supplied to the gate electrode of one field effect transistor and the inverted input signal can be supplied to the gate electrode of the other field effect transistor.