Power buffer circuit

• US 4,728,901 A
• Filed: 04/07/1986
• Issued: 03/01/1988
• Est. Priority Date: 04/07/1986
• Status: Expired due to Term

• Current Assignee: St Clair Intellectual Property Consultants Incorporated
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Pepper, Steven H.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US06/848,520
• Time in Patent Office: 694 Days
• Field of Search: 330/85, 330/260, 330/300, 330/253, 307/297, 307/475, 323/273, 323/280, 323/281
• US Class Current: 330/260
• CPC Class Codes: H03F 3/505 with field-effect devices

Abstract

A power buffer circuit includes a power MOS device connected via a local feedback loop to a differential amplifier. The MOS device amplifies the power of an input signal to produce an output signal. The differential amplifier causes the output signal voltage to follow the input signal voltage by sensing a difference between the two voltages and generating in response a difference signal to the MOS device to change the output signal voltage level. The buffer circuit may be configured as a current source or a current sink that maintains unity voltage gain from the input to output signal. The power buffer circuit may be incorporated into a voltage regulator that maintains a remotely sensed output voltage substantially equal to a predetermined factor of a reference voltage via a second, outer feedback loop.

Claims

1. A power buffer circuit for providing current gain to an input signal while maintaining substantially unity voltage gain between the input and output signals, comprising:

an MOS device haivng a gate, drain, and source, the output signal appearing at the source; and

a bipolar transistor having its emitter for sensing the input voltage, its base connected directly to the source to sense the output voltage and its collector coupled to the gate,

the bipolar transistor setting the voltage on the gate in response to a difference between the input and output voltages to cause the output voltage to follow the input voltage by varying the current through the MOS device.

2. A power buffer circuit for providing current gain to an input signal while maintaining substantially unity voltage gain between the input signals, comprising:

an MOS device having a gate, drain, and source, the output signal appearing at the drain; and

a bipolar transistor having its base for sensing the input voltage, its emitter connected directly to the drain to sense the output voltage and its collector coupled to the gate,

the bipolar transistor setting the voltage on the gate in response to a difference between the input and output voltages to cause the output voltage to follow the input voltage by varying the current through the MOS device.

3. The power buffer circuit of claim 2 including a voltage level shifting means connected between the collector and the gate for level shifting the gate voltage.

4. A voltage regulator for regulating a voltage supply to provide an out voltage that follows a reference voltage, comprising:

a metal oxide semiconductor device for amplifying to power of an input signal to produce an output signal;

a bipolar transistor directly connected to the MOS device in feedback relation for adjusting the metal oxide semiconductor device to cause the output signal voltage to follow the input signal voltage, the transistor sampling the output signal voltage and the input signal voltage to sense a difference beteen the signal voltages and in response to such a difference signaling the MOS device to change the output voltage;

sensing means for sensing the output signal voltage remote from the amplifying means; and

a differential amplifer for comparing the reference voltage to the remotely sensed output voltage and generating in response an error signal that forms the input signal to the bipolar transistor,

the remotely sensed output voltage level thereby maintained substantially equal to a predetermined factor of the reference voltage level while the level of the voltage supply is allowed to fluctuate.

5. The voltage regulator of claim 4 in which the MOS device has a gate, drain, and source and the bipolar transistor has a colector, base, and emitter, the voltage supply connected to the drain, the source connected to the base, the gate connected to the collector, and the emitter receiving the error signal from the differential amplifier.

6. The voltage regulator of claim 4 including a Zener diode, the MOS device having a gate, drain, and source and the bipolar transistor having a collector, base, and emitter, the voltage supply connected to the source, the drain connected to the emitter, the gate connected to the collector, and the base receiving the errro signal from the differential amplifier, the Zener diode connected between the collector and the gate to level shift the gate voltage.