Charge redistribution capacitance detection apparatus

• US 4,728,931 A
• Filed: 07/25/1986
• Issued: 03/01/1988
• Est. Priority Date: 07/25/1986
• Status: Expired due to Fees

• Current Assignee: Key Tronic Corporation, Inc.
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Linder, William J., Reinke, James D.
• Primary Examiner(s): Caldwell, Sr., John W.
• Assistant Examiner(s): Queen, Tyrone
• Application Number:
  US06/890,215
• Time in Patent Office: 585 Days
• Field of Search: 340/365 C, 340/365 S, 340/365 R, 324/60 CD, 178/17 C, 307/116, 200/DIG. 1
• US Class Current: 341/25
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: H03K 17/9622 using a plurality of detectors, e.g. keyboard
• CPC Class Codes: H03K 2017/9613 using two electrodes per touch switch
• CPC Class Codes: H03K 5/249 using clock signals

Abstract

A charge redistribution capacitance detector is disclosed for detecting whether the capacitance of a variable capacitor is smaller or larger than that of a reference capacitor. First plates of the variable and reference capacitors are connected to a sense node, and a switching device responsive to a clock signal periodically impresses a reference voltage on the sense node during one phase of the clock signal and allows the sense node to electrically float during the alternate phase of the clock signal. Second plates of the sense and reference capacitors are alternately charged and discharged by equal voltage differences in opposite senses during successive clock phases. The voltage on the first plates of the capacitors changes in a sense dependent on the relative capacitance values of the capacitors and is compared with the reference voltage by a comparator which produces a corresponding detector output.

Claims

1. A charge redistribution capacitance detector for determining the capacitance of a sample capacitor relative to a predetermined capacitance value, comprising:

a sense node;

a reference capacitor having first and second plates and a capacitance equal to the predetermined capacitance value, the first plate of said reference capacitor being connected to said sense node;

first connecting means adapted to connect a first plate of the sample capacitor to the sense node;

a source of reference voltage;

a comparator having an input terminal, and an output terminal at which is produced an output signal indicative of whether the voltage at the input terminal is smaller or larger than the reference voltage;

signal generating means operable to impress the reference voltage and drive voltage different from the reference voltage on the second plates of said sample and reference capacitors respectively during first time periods, and to impress the drive voltage and the reference voltage on the second plates of said sample and reference capacitors respectively during second time periods which alternate with the first time periods;

second connecting means connecting the input terminal of said comparator to said sense node; and

first switching means operable to electrically connect said sense node to said source of reference voltage during the first time periods, and to isolate said sense node from said source of reference voltage during the second time periods.

2. The capacitance detector of claim 1 wherein said second connecting means comprises second switching means operable to electrically connect the input terminal of said comparator to said sense node during the second time periods and to isolate the input terminal of said comparator from the sense node during the first time periods.

3. The capacitance detector of claim 2 including third switching means operable to impress the reference voltage on the input terminal of said comparator during the first time periods.

4. The capacitance detector of claim 3 wherein said comparator includes nulling circuitry operable to adjust said comparator during the first time periods to cause it to produce a null output signal when the reference voltage is impressed on the input terminal of said comparator.

5. The capacitance detector of claim 4 including a latch circuit connected to the output terminal of said comparator, said latch circuit being operable to transmit the comparator output signals during each second time period, and to continue to produce an output signal corresponding to the comparator output signal during the next succeeding first time period.

6. The capacitance detector of claim 5 including a time-out circuit operable to render said second switching means electrically nonconductive, null the output of said comparator and cause said latching circuit to continue to produce the output signal then being produced if a second time period exceeds a predetermined duration.

7. A charge redistribution capacitance detector for determining the capacitance of a sample capacitor relative to a reference capacitance value, comprising:

a reference capacitor having a capacitance equal to the reference capacitance value, and having first and second plates of which the first plate is adapted to be connected to a first plate of the sample capacitor at a sense node;

a reference voltage source;

a clock generator operable to produce a clock signal having first and second states during alternate first and second time intervals respectively;

voltage supply means responsive to the clock signal for producing first and second electrical signals, the first electrical signal being the reference voltage and a drive voltage different from the reference voltage during the first and second time intervals respectively, the second electrical signal being identical to the first electrical signal, but shifted in time therefrom by substantially the duration of the first time intervals;

first connecting means for supplying the first and second electrical signals from said voltage supply means to the second plates of said sample and reference capacitors respectively so that, during the first time intervals, the second plates of the sample and reference capacitors are charged to the reference and drive voltages respectively, and during the second time intervals, the second plates of the sample and reference capacitors are charged to the drive and reference voltages respectively;

first switching means responsive to the clock signal for electrically connecting the sense node to the reference voltage source during the first time intervals and electrically isolating the sense node from the reference voltage source during the second time intervals;

a comparator having an input terminal, and an output terminal at which is produced an output signal indicative of whether the voltage at the input terminal is smaller or larger than the reference voltage; and

second switching means responsive to the clock signal for electrically isolating the input terminal of said comparator from the sense node during the first time intervals and electrically connecting the sense node to the input terminal of said comparator during the second time intervals, whereby the output signal of said comparator during the second time intervals is indicative of the capacitance of the sample capacitor relative to the reference capacitance value.

8. Capacitive keyboard apparatus comprising:

an array of capacitive key switches including pluralities of columns and rows of said switches, each switch including a sense capacitor having first and second plates and minimum and maximum capacitance values;

a reference capacitor having a capacitance between the minimum and maximum capacitance values of the sense capacitors;

a reference voltage source;

a clock generator operable to produce a clock signal having first and second states during alternate first and second time periods respectively;

a signal generator responsive to the clock signal and operable to produce first and second electrical signals, the first electrical signal being the reference voltage and a drive voltage different from the reference voltage during the first and second time intervals respectively, the second electrical signal being substantially identical to the first electrical signal, but shifted in time therefrom by substantially the duration of the first time intervals;

first scanning means responsive to the clock signals and operable during the first time intervals to electrically connect the first plates of the sense capacitors and the first plate of said reference capacitor to said reference voltage source during the first time intervals and to sequentially electrically isolate the first plates of columns of the sense capacitors and the first plate of said reference capacitor from said reference voltage source during the second time intervals;

second scanning means responsive to the clock signals for supplying the first and second electrical signals from said signal generator sequentially to the second plates of rows of the sense capacitors and to the second plate of said reference capacitor respectively, whereby, during each first time interval, the second plates of a row of the sense capacitors are charged to the reference voltage and the second plate of the reference capacitor is charged to the drive voltage, and, during each second time interval, the second plates of a row of the sense capacitors are charged to the drive voltage and the second plate of the reference capacitor is charged to the reference voltage;

a comparator having an input terminal, and an output terminal at which is produced a output signal indicative of whether the voltage at the input terminal is smaller or larger than the reference voltage; and

first switching means responsive to the clock signal for electrically isolating the input terminal of said comparator from the first plates of the sense and reference capacitors during the first time intervals and electrically connecting the input terminal of said comparator to the first plates of columns of the sense capacitors and the reference capacitor during the second time intervals, whereby said comparator produces an output signal sequentially indicative of the states of the capacitive switches in said array.

9. Capacitive keyboard apparatus comprising:

an array of capacitive key switches, each including a sense capacitor having first and second plates and minimum and maximum capacitance values;

a sense node;

a reference capacitor having first and second plates and a capacitance between the minimum and maximum capacitance values of the sense capacitors, the first plate of said reference capacitor being connected to said sense node;

a source of reference voltage;

a clock generator operable to produce a periodic clock signal having first and second states during alternate first and second time intervals;

scanning means responsive to the clock signal for sequentially addressing the sense capacitors, each sense capacitor being addressed for a period comprising a successive first and second time interval, said scanning means being operable to electrically connect the first plate of said sense capacitor to said source of reference voltage and to said sense node during the first time interval and to electrically isolate the first plate of said sense capacitor from said source of reference voltage during the second time interval, said scanning means further being operable to impress the reference voltage and a drive voltage different from the reference voltage on the second plates of the sense and reference capacitors respectively during the first time interval and to impress the drive voltage and the reference voltage on the second plates of the sense and reference capacitors respectively during the second time interval;

a comparator having an input terminal, and an output terminal at which is produced a signal indicative of whether the voltage at the input terminal is smaller or larger than the reference voltage; and

first switching means responsive to the clock signal to electrically isolate the input terminal of said comparator from said sense node during the first time intervals and to electrically connect the input terminal of said comparator to said sense node during the second time intervals.

10. The capacitive keyboard apparatus of claim 9 including second switching means responsive to the clock signal for electrically connecting the input terminal of said comparator to said source of reference voltage during the first time intervals.

11. The capacitive keyboard apparatus of claim 10 wherein said comparator includes nulling circuitry responsive to the clock signal to adjust said comparator during the first time intervals to cause it to produce a null output signal when the input terminal of said comparator is electrically connected to said source of reference potential.

12. The capacitive keyboard apparatus of claim 11 including a latch circuit connected to the output terminal of said comparator, said latch circuit being responsive to the clock signal and operable to transmit the output signal of said comparator during each second time interval and to continue to transmit said output signal during the next succeeding first time interval.

13. The capacitive keyboard apparatus of claim 12 including a time-out circuit operable to cause operation of the nulling circuitry in said comparator and operation of the latch circuit in the event a second time interval exceeds a predetermined duration.