Jitter correction circuit

• US 4,729,025 A
• Filed: 10/21/1986
• Issued: 03/01/1988
• Est. Priority Date: 11/06/1985
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Yanase, Shuji
• Primary Examiner(s): Chin, Tommy P.
• Application Number:
  US06/921,083
• Time in Patent Office: 497 Days
• Field of Search: 358/166, 358/160, 358/167, 358/336, 358/337, 358/339, 358/340, 358/342, 358/13, 358/19, 358/312, 358/320, 358/321, 358/324
• US Class Current: 348/537
• CPC Class Codes: H04N 5/95 Time-base error compensation H04N5/932 takes precedence

Abstract

A jitter correction circuit is a circuit for suppressing a jitter contained in a reproduced digital signal. This jitter correction circuit comprises a phase-locked loop circuit comprising a phase comparing circuit (9), a second low-pass filter (10), a second voltage control oscillator (11) and a second frequency dividing circuit (12). The phase-locked loop circuit provides an oscillation output which causes little influence to a jitter component contained in a reproduced signal digitally converted by an analog-to-digital converting circuit (1). The digitally converted reproduced signal is resampled in a sampling pulse generating circuit (13) and a resampling circuit (7) which operates based on the above stated phase-locked loop circuit. As a result, the resampling circuit (7) provides an output having a considerably decreased amount of jitter.

Claims

1. A jitter correction circuit comprising:

analog-to-digital converting circuit converts an input reproduced compressed video signal to a digital signal based on an input clock pulse;

a phase deviation detection circuit connected to said analog-to-digital converting circuit, said phase deviation detection circuit latches said digital signal and detects an amount of deviation of said digital signal, said phase deviation detection circuit producing a phase deviation;

digital-to-analog converting circuit converts said phase deviation to an analog signal;

a first low-pass filter connected to said digital-to-analog converting circuit, said first low-pass filter setting a cut-off frequency of said analog signal approximately equal to a horizontal synchronizing signal;

a first control oscillation circuit receives said horizontal synchronized signal from said first low-pass filter and provides a first oscillation output having a rapid frequency response characteristic based on said phase deviation of said horizontal synchronized signal contained in said reproduced compressed video signal;

a timing pulse generating circuit receives said first oscillation output from said first control oscillation circuit and produces said clock pulse input to said analog-to-digital converting circuit, wherein said analog-to-digital converting circuit samples said reproduced video signal based on said first oscillation output to provide said digital signal by analog-to-digital conversion;

a second oscillation control circuit provides a second oscillation output having a stable frequency response characteristic based on at least one of a phase deviation of said horizontal synchronized signal and a phase deviation of said first oscillation output; and

a resampling circuit resamples said digital signal from said analog-to-digital converting circuit based on said second oscillation output.

2. A jitter correction circuit in accordance with claim 1, wherein

4. A jitter correction circuit in accordance with claim 1, wherein

said second oscillation control circuit comprises a phase-locked loop circuit comprising a phase comparing circuit for receiving as a reference input at least one of said first oscillation output and a frequency divided output thereof and receiving as an input to be compared at least one of said second oscillation output feedback and a frequency divided output thereof;

a limiting circuit for limiting an output of said phase comparing circuit within a predetermined range;

a low-pass filter having a low cut-off frequency for receiving an output of said limiting circuit; and

a variable oscillation circuit for receiving an output of said low-pass filter as a control input.

6. A jitter correction circuit in accordance with claim 1, wherein

said reproduced video signal comprises a reproduced compressed video signal obtained by compressing a band of a high-quality video signal.

8. A jitter correction circuit in accordance with claim 1, wherein

said first control oscillation circuit controls frequency of said first oscillation output based on said digital signal with said first clock pulse for generating said reproduced horizontal synchronizing signal.

10. A jitter correction circuit in accordance with claim 8, wherein

said second oscillation control circuit comprises a phase-locked loop circuit comprising:

a phase comparing circuit for receiving said first oscillation output as said reference input and said second clock feedback as a comparison input;

an output limiting circuit for limiting an output of said phase comparing circuit within a predetermined range;

a low-pass filter having a low cut-off frequency receiving an output of said output limiting circuit; and

a variable oscillation circuit for receiving an output of said low-pass filter as a control input.

11. A jitter correction circuit in accordance with claim 8, wherein

said second oscillation control circuit comprises a phase-locked loop circuit comprising:

a phase comparing circuit for receiving said first oscillation output as said reference input and said second clock feedback as a comparison input;

a low-pass filter having a low cut-off frequency for receiving an output of said phase comparing circuit;

a limiter for limiting an output level of said low-pass filter within a predetermined range; and

a variable oscillation circuit for receiving an output of said limiter as a control input.

3. said second oscillation control circuit comprises a phase-locked loop circuit comprising:

a phase comparing circuit for receiving as a reference input at least one of said first oscillation output and a frequency divided output thereof and receiving as an input to be compared, at least one of said second oscillation output feedback and a frequency divided output thereof;

a low-pass filter having a low cut-off frequency for receiving an output of said phase comparing circuit;

a limiter for limiting an output of said low-pass filter within a predetermined range; and

a variable oscillation circuit for receiving an output of said limiter as a control input.

5. A jitter correction circuit in accordance with claim 3, wherein

said phase comparing circuit comprises an AND gate circuit for receiving a frequency divided output of said first oscillation output and a frequency divided output of said second oscillation output and said limiting circuit comprises a pulse width limiting circuit for limiting a pulse width of said output of said phase comparing circuit within a predetermined range.

7. A jitter correction circuit in accordance with claim 5, wherein

said reproduced compressed video signal being reproduced for reproducing stored information optically.

9. A jitter correction circuit comprising:

analog-to-digital converting circuit converts an input reproduced compressed video signal to a digital signal based on a first clock pulse input;

a phase deviation detection circuit connected to said analog-to-digital converting circuit, said phase deviation detection circuit latches said digital signal and detects an amount of deviation of said digital signal, said phase deviation detection circuit producing a phase deviation;

a digital-to-analog converting circuit converts said phase deviation to an analog signal;

a low-pas filter connected to said digital-to-analog converter, said low-pass filter setting a cut-off frequency of said analog signal to a horizontal synchronized signal;

a first oscillation control circuit receives said horizontal synchronized signal from said low-pass filter and provides a first oscillation output having a rapid frequency response characteristic based on said phase deviation of said horizontal synchronized signal contained in said reproduced compressed video signal;

a timing pulse generating circuit receives said first oscillation output from said first oscillation control circuit and produces said first clock pulse input to said analog-to-digital converting circuit, wherein said analog-to-digital converting circuit samples said reproduced video signal based on said first oscillation output to provide said digital signal by analog-to-digital conversion;

a second oscillation control circuit receives said first oscillation output as a reference input and provides a second clock having a stable frequency;

a serial-to-parallel converting circuit converts said digital signal as serial data from said analog-to-digial converting circuit to parallel data based on said first clock pulse from said timing pulse generating circuit, said serial-to-parallel converting circuit including a latching means for latching said converted parallel digital data based on a frequency divided output of said first clock pulse; and

a parallel-to-serial converting circuit latches an output of said latching means based on a frequency divided output of said second clock from said second oscillation control circuit, said parallel-to-serial converting circuit converting said parallel data to serial data based on said second clock.