Method and apparatus for coordinating execution of an instruction by a coprocessor

• US 4,729,094 A
• Filed: 03/24/1987
• Issued: 03/01/1988
• Est. Priority Date: 04/18/1983
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Zolnowsky, John, MacGregor, Douglas B., Mothersole, David S., Moyer, William C.
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US07/030,241
• Time in Patent Office: 343 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/34
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3881 Arrangements for communication of instructions and data

Abstract

A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Claims

1. A method for a first data processor to coordinate, via a communication bus, execution by a second data processor of an instruction received by said first processor for execution thereby, using only standard bus cycles on said communication bus, said instruction including a type field indicative of instruction type, the method comprising the steps of:

receiving said instruction;

writing to said second processor at a unique address within the address space of said first processor, using said standard common bus cycles, at least the type field of said received instruction;

immediately reading a response from said second processor at said unique address using said standard bus cycles after said second processor has received said type field on said received instruction;

examining said response;

selectively performing a predetermined task selected by said response when said response indicates that said task must be performed by said first processor in support of the execution of said instruction by said second processor;

but

vectoring to a predetermined exception handler when said response selects a task other than said predetermined task must be performed by said first processor in support of the execution of said instruction by said second processor.

2. The method of claim 1 wherein the step of performing said task comprises performing a particlar one of a plurality of predetermined tasks selected by said response;

and wherein said step of vectoring comprises vectoring to said exception handler if a task other than one of said plurality of predetermined tasks is selected by said response.

3. The method of claim 1 wherein said step of reading comprises repeatedly reading a response from said second processor until said response indicates that said second processor is not busy.

4. The method of claim 3 wherein the step of performing said task comprises performing a particular one of a plurality of predetermined tasks selected by said response;

and wherein said step of vectoring comprises vectoring to said exception handler if a task other than one of said plurality of predetermined tasks is selected by said response.

5. The method of claim 1 further comprising the step of repeating the steps of reading said response and performing said tasks until said response indicates that no further tasks must be performed by said first processor in support of the execution of said instruction by said second processor.