Coaxial shielded helical delay line and process

• US 4,729,510 A
• Filed: 11/14/1984
• Issued: 03/08/1988
• Est. Priority Date: 11/14/1984
• Status: Expired due to Fees

• Current Assignee: ITT Corporation (ITT, Inc.)
• Original Assignee: ITT Corporation (ITT, Inc.)
• Inventors: Landis, Richard C.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Lee, Benny T.
• Application Number:
  US06/671,272
• Time in Patent Office: 1,210 Days
• Field of Search: 333/162, 333/163, 333/161, 333/156, 333/140, 315/315, 315/3.6, 315/39.3, 315/39, 29/600, 29/602 R, 29/825, 29/828, 29/829, 29/842, 336/200, 174/68.5, 156/150, 156/901
• US Class Current: 333/162
• CPC Class Codes: H01P 9/02 Helical lines
• CPC Class Codes: Y10T 29/49016 Antenna or wave energy "plumbing" making
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.

Abstract

A substrate is disclosed with a shielded delay line imbedded therein to obtain a delay of a preselected duration. The delay line comprises a conductor formed in the shape of a helical coil to reduce its overall dimension. The substrate is formed by superimposing a plurality of layers of conductive and/or dielectric material to form a preselected profile.

Claims

1. A method of forming a shielded delay line embedded in a planar substrate formed of a plurality of superimposed parallel planar layers, said substrate having a major surface thereof lying in a plane parallel to said planar layers, comprising the steps of:

providing a first conductive planar layer as a first of said plurality of superimposed parallel planar layers;

forming a pair of conductive strips in a next one of said superimposed parallel planar layers disposed on said first conductive layer;

placing dielectric material between said conductive strips;

forming a plurality of conductive strips in a plurality of successive ones of said plurality of superimposed parallel planar layers over said next one of said superimposed parallel planar layers;

placing dielectric material between the conductive strips in each of said plurality of successive ones of said plurality of superimposed parallel planar layers;

forming a pair of conductive strips in an additional one of said superimposed parallel planar layers on said plurality of successive planar layers;

depositing dielectric material between said conductive strips of the additional one of said superimposed parallel planar layers; and

forming a second conductive planar layer over said additional one of said superimposed parallel planar layers, selected ones of said plurality of conductive strips formed in the plurality of superimposed parallel planar layers being at least partially overlapping and electrically connected and arranged to form a coil having a plurality of turns disposed about and extending along an axis parallel to said plane of said planar substrate, said first and second conductive planar layers, said pairs of conductive strips and others of said plurality of conductive strips being at least partially overlapping and electrically connected and arranged to form a conductive shield spaced from said coil and extending along the length thereof.

2. A delay line, embedded in a planar substrate formed of a plurality of superimposed parallel planar layers, said substrate having a major surface thereof lying in a plane parallel to said planar layers, comprising:

a plurality of conductive portions in said superimposed parallel planar layers;

a coil having a plurality of turns embedded in said substrate and formed about an axis positioned parallel to said plane, each of said turns being formed of at least partially superimposed and electrically connected ones of said conductive portions of said plurality of superimposed parallel planar layers;

dielectric material disposed between the turns of said coil and embedding said coil; and

a conductive shield spaced from, extending along the axis of and substantially enclosing said coil, said shield being formed in said substrate by at least partially superimposed and electrically connected other ones of said conductive portions of said plurality of superimposed parallel planar layers.

3. A method of forming a delay line embedded in a planar substrate formed of a plurality of superimposed parallel planar layers, said substrate having a major surface thereof lying in a plane parallel to said planar layers, comprising the steps of:

forming and electrically connecting a plurality of conductive strips arranged in said plurality of planar layers to form a coil having a plurality of turns disposed about an axis parallel to said plane;

placing a dielectric between said turns and embedding said coil; and

forming and arranging additional conductive strips in said plurality of planar layers to provide a conductive shield spaced from, extending along the axis of and substantially enclosing said coil.

4. A method of forming a delay line embedded in a planar substrate formed of a plurality of superimposed parallel planar layers, said substrate having a major surface thereof lying in a plane parallel to said planar layers, comprising the steps of:

forming a plurality of conductive strips in a first of said plurality of superimposed parallel planar layers;

forming additional conductive strips in a plurality of additional ones of said plurality of superimposed parallel planar layers, said conductive strips being formed and arranged in at least a partially superimposed and electrically connected manner to form a coil having a plurality of turns disposed about an axis parallel to said plane; and

forming additional conductive strips in said plurality of superimposed parallel planar layers, said additional conductive strips being arranged to provide a conductive shield spaced from, substantially enclosing and coextensive with said coil.