Semiconductor wafer dicing techniques

• US 4,729,971 A
• Filed: 03/31/1987
• Issued: 03/08/1988
• Est. Priority Date: 03/31/1987
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Microwave Semiconductor Corporation
• Inventors: Coleman, Basil
• Primary Examiner(s): Chaudhuri, Olik
• Application Number:
  US07/033,132
• Time in Patent Office: 343 Days
• Field of Search: 148/DIG. 51, 156/645, 437/226, 437/227
• US Class Current: 438/462
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304

Abstract

A dice separation technique involves producing a depressed street pattern (14) on the front device processing major surface of a wafer (11) before thinning the wafer down to a desired thickness. After mounting the wafer (11) on a suitable carrier, it is thinned down and selectively metallized to from backside contacts. Semiconductor material is removed from the central regions of the streets (14). Exposed material damaged by the material removal is also removed to eliminate micro-cracking while producing dice (12 and 13) having straight and smooth orthogonal edges. The present technique is particularly suitable for working with brittle compound semiconductor material between die areas having FETs or MMICs embedded therein.

Claims

1. A method for separating a wafer of III-V compound semiconductor material into dice wherein the wafer has at least some repetitious device geometries embedded into a first of two major surfaces corresponding to dice areas, the method comprising the steps of:

defining a first patterned mask on the first major surface, the first patterned mask having open areas in the form of lanes generally intersecting conforming to regions between dice geometries and closed areas conforming to the regions occupied by the dice areas;

etching the lanes to a depth below the plane of the first major surface;

removing the first patterned mask from the first major surface;

mounting the wafer on the first major surface so that the second of the two major surfaces is exposed;

defining a metallized pattern on the second major surface aligned with the dice areas on the first major surface;

removing semiconductor material from the lanes on the second major surface to form dice from the wafer; and

etching exposed semiconductor material remaining in the lanes to remove semiconductor material immediately adjacent to the previously removed material.

2. The method of claim 1, wherein the step of defining a first patterned mask includes the steps of:

coating the first major surface with a photoresist material;

exposing the photoresist with a light source through a mask; and

removing the photoresist to form the open regions.

3. The method of claim 1, wherein the step of etching comprises wet chemical etching.

4. The method of claim 1, wherein the step of etching comprises reactive ion etching.

5. The method of claim 1, wherein the step of removing semiconductor material comprises sawing the lanes in a path corresponding to their central region.

6. The method of claim 1, wherein the step of removing semiconductor material comprises laser scribing the lanes in a path corresponding to their central region.

7. The method of claim 1, wherein the step of etching semiconductor material remaining in the lanes comprises wet chemical etching with an isotropic etch solution.

8. The method of claim 1, wherein the step of defining a metallized pattern comprises defining a second patterned mask on the second major surface to provide exposed portions aligned with the lanes on the first major surface, etching the exposed portions to form slightly depressed lanes in the second major surface, coating the second major surface with at least one layer of metal, masking the slightly depressed lanes with an insulative coating, and plating exposed portions of the second major surface to produce a backside metallized contact suitable for subsequent mounting of the dice.

9. The method of claim 4, wherein the wafer of semiconductor material comprises gallium arsenide and the step of reactive ion etching involves using a chlorine based plasma.

10. The method of claim 7, wherein the wafer of semiconductor material comprises gallium arsenide and the isotropic etch solution comprises H₂ SO₄ :

H₂ O₂ ;

H₂ O in respective portions of 3;

1;

1.

11. The method of claim 8, wherein the step of defining a second patterned mask on the second major surface utilizes infrared alignment of the second patterned mask to the lanes etched into the first major surface.

12. The method of claim 9, wherein the chlorine based plasma comprises SiCl₄.