Integrated circuit having fuse circuit

• US 4,730,129 A
• Filed: 02/21/1985
• Issued: 03/08/1988
• Est. Priority Date: 02/29/1984
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kunitoki, Tadayoshi, Gotoh, Kunihiko
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US06/703,987
• Time in Patent Office: 1,111 Days
• Field of Search: 307/363, 307/362, 307/202.1, 307/303, 307/231, 365/200, 365/201, 365/96
• US Class Current: 327/525
• CPC Class Codes: G11C 17/16 using electrically-fusible links

Abstract

This invention is related to an integrated circuit (IC) having a fuse circuit. In such an IC device, it is very difficult to hold a specific gain of the IC because of a leakage of a gap between the fuse terminals called "re-glown fuse" or "glown-back fuse", and the IC suffers from malfunction. The present invention provides a fuse circuit to detect whether a fuse has been blown or not, by judging whether the fuse resistance is larger or smaller compared to a predetermined threshold resistor, which generates a judging potential corresponding to a fuse condition. Thus the IC can be used without malfunction.

Claims

1. A detection circuit for an integrated circuit having a fuse with first and second terminals and said detection circuit for detecting whether the fuse has blown, said detection circuit comprising:

a first voltage source supplying a first voltage;

a second voltage source, coupled to the first terminal of the fuse, supplying a second voltage lower than the first voltage;

a first circuit comprising a first transistor, having a source coupled to the second terminal of the fuse and a gate coupled to the first terminal of the fuse; and

a second circuit comprising;

a second transistor having a source and a gate; and

a resistor, coupled between the source and gate of said second transistor, said first and second circuits being coupled in series between said first and second voltage sources at a junction point, generating a detection signal, indicating whether the fuse has been blown, at said junction point.

2. a circuit as set forth in claim 1, wherein the resistance of said resistor is equivalent to that of said fuse when said fuse has not been blown.

3. A circuit as set forth in claim 1, wherein said first and said second transistors comprise depletion type transistors.

4. An integrated circuit as set forth in the claim 1, wherein said first transistor is an enhancement type transistor, and means are provided for holding the gate thereof at a constant potential.

5. A detection circuit for an integrated circuit having a fuse which has first and second terminals, said detection circuit detecting whether the fuse has blown, said detection circuit comprising:

a first voltage source supplying a first voltage;

a second voltage source, coupled to the first terminal of the fuse, supplying a second voltage lower than the first voltage;

a first circuit, comprising a first transistor having a source coupled to the second terminal of the fuse and a gate coupled to the first terminal of the fuse; and

a second circuit, comprising a second transistor having a source and a gate coupled to each other, said first and said second circuits being coupled in series between said first and said second voltage sources at a junction point and generating a detection signal, indicating whether the fuse has been blown, at said junction point.

9. A circuit as recited in claim 5, wherein said first and said second transistors are depletion type transistors.

11. A circuit as recited in claim 5, wherein said first and said second transistors each have a channel width W and a channel length L and where the ratio W/L of said second transistor is smaller than that of said first transistor.

6. A detection circuit for an integrated circuit having a fuse which has first and second terminals and said detection circuit detects whether or not said fuse has blown, said detection circuit comprising:

a first voltage source supplying a first voltage;

a second voltage source, coupled to the first terminal of the fuse, supplying a second voltage lower than the first voltage;

a first circuit comprising a first transistor, having a source coupled to the second terminal of the fuse; and

a second circuit comprising a second transistor, having a source and a gate;

a mirror circuit comprising a third transistor, a fourth transistor, and an impedance element, said third and said fourth transistors each having a gate, a source, and a drain, the sources of said third and said fourth transistors being connected to said first voltage source, the gates of said third and said fourth transistors being coupled to each other, the gate of said fourth transistor being further connected to the drain of said fourth transistor, said impedance element being connected between the drain of said fourth transistor and said second circuit, said first circuit being connected between the drain of said third transistor and said second voltage source, said second circuit being connected between said impedance element and said second voltage source, the gates of said first and said second transistors being connected to each other, and said first and said second circuits being coupled in parallel with each other and coupled to said mirror circuit, a detection signal indicating a blown condition of said fuse being generated at the drain of said third transistor.

7. A circuit according to claim 6, further comprising a resistor coupled between the source of said second transistor and the second voltage source.

8. A circuit as recited in claim 7, wherein the resistance of said resistor is equivalent to that of said fuse when said fuse has not been blown.

10. A circuit as recited in claim 6, wherein said first, said second, said third, and said fourth transistors are enhancement type transistors.

12. A circuit as recited in claim 6, wherein said first and said second transistors each have a channel width W and a channel length L and where the ratio W/L of said second transistor is smaller than that of said first transistor.