Method and apparatus for coordinating execution of an instruction by a selected coprocessor

• US 4,731,736 A
• Filed: 09/18/1986
• Issued: 03/15/1988
• Est. Priority Date: 04/18/1983
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Zolnowsky, John, MacGregor, Douglas B., Mothersole, David
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US07/086,351
• Time in Patent Office: 544 Days
• Field of Search: 364/200, 364/900, 364/715
• US Class Current: 710/110
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3881 Arrangements for communication of instructions and data

Abstract

A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Claims

1. A first data processor adapted for coordinating the execution of an instruction received for execution by said first processor with a second data processor responsive to a unique address comprised of a general address portion and a value unique to the second data processor contained in an address field of said instruction, the first data processor comprising:

first means for receiving said instruction;

second means for providing said unique address by combining said general address portion and the value contained in said address field of said received instruction; and

third means for coordinating the execution of said instruction by said second processor at the address provided by said second means.

2. The data processor of claim 1 wherein said second data processor is further characterized as containing a plurality of registers which may be required by said second data processor in the execution of said instruction, with each of said registers being responsive to a respective address within a range of addresses unique to said second data processor;

and wherein said second means provides said respective addresses as each of said registers is required by said third means in coordinating the execution of said instruction by said second data processor.