Autoranging time stamp circuit

• US 4,731,768 A
• Filed: 09/15/1986
• Issued: 03/15/1988
• Est. Priority Date: 09/15/1986
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Easterday, John L.
• Primary Examiner(s): Miska, Vit W.
• Application Number:
  US06/906,873
• Time in Patent Office: 547 Days
• Field of Search: 368/113, 368/118-121, 377/20, 371/20, 371/21, 371/24, 371/25, 324/78 R, 324/78 D, 324/79 R, 324/79 D
• US Class Current: 368/118
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware

Abstract

A time stamp circuit comprises a plurality of counter programmable logic arrays for providing a Gray code count. Each count provided by the counters is associated as a time value with a specified event to be stored in memory. The count is generated automatically over a range of progressively slower frequencies provided by frequency dividing circuitry connected to an oscillator. The circuit has two modes of operation, a cumulative mode and a delta mode. In the cumulative mode, the count begins with the first occurrence of a specified event and ends when acquisition is halted. In the delta mode, a control programmable logic array automatically resets the Gray code count and thereby the clock frequency to its highest frequency each time a specified event is stored. The resolution, or time between counts, therefore is the same to begin between each pair of events.

Claims

1. A circuit for associating time values with specified events stored in a memory, comprising:

means for generating a plurality of different known clock frequencies;

means for selecting in order of decreasing frequency the clock frequencies to provide a clock signal;

means for generating in response to the clock signal a binary code count to be associated as a time value with each specified event to be stored;

means for signaling the occurrence of a specified event; and

control means responsive to the signaling means to reset the clock frequency to its initial frequency in the predetermined order each time a specified event occurs.

2. The circuit of claim 1 in which a portion of the binary code count is fed back to the frequency selecting means to select the clock frequencies in the predetermined order.

3. The circuit of claim 2 in which the control means resets the binary code count in response to the signaling of a specified event, the portion of the reset count fed back to the frequency selecting means thereby selecting the initial frequency.

4. The circuit of claim 1 including means for comparing the binary code counts associated with at least two specified events to determine the time elapsed between the events.

5. The circuit of claim 1 in which the clock frequency generating means includes an oscillator providing a clock signal of a predetermined clock frequency to a plurality of counters connected in cascade, the counters dividing the predetermined frequency to generate the plurality of clock frequencies.

7. The circuit of claim 1 in which the binary code is a reflected code.

8. The circuit of claim 1 in which the clock frequencies range from one hertz to five megahertz.

9. The circuit of claim 1 in which the binary code generating means comprises a plurality of programmable logic arrays and the control means comprises a programmable logic array, the control programmable logic array enabling the counter programmable logic arrays to count simultaneously in generating the binary code count.

10. The circuit of claim 1 including means for warning that two specified events have occurred too close in time to generate binary code counts that validly reflect the time therebetween.

6. A circuit for associating time values with specified events stored in a memory, comprising:

means for generating a plurality of different known clock frequencies;

a multiplexer for selecting in order of decreasing frequency the clock frequencies to provide a clock signal;

means for generating in response to the clock signal a binary code count to be associated as a time value with each specified event to be stored;

means for signaling the occurrence of a specified event; and

control means responsive to the signaling means to reset the clock frequency to its initial frequency in the predetermined order each time a specified event occurs.

11. In a data acquisition system that stores specified events in memory, a circuit for associating a time value with each specified event that is stored for measuring the time between the events, the circuit comprising:

an oscillator providing a clock frequency;

a plurality of counters clocked by the oscillator and connected in cascade to divide the oscillator frequency, each counter generating a clock signal of predetermined frequency, the frequencies having a decreasing order;

a plurality of counter programmable logic arrays for generating a Gray code count, the count generated in response to a clock signal provided by one of the predetermined frequencies;

a multiplexer for selecting in response to a portion of the Gray code count the clock frequencies in the decreasing order to provide the clock signal to the counter programmable logic arrays; and

a control programmable logic array for sensing the occurrence of a specified event and in response resetting the Gray code count to an initial count and through the reset of the count resetting the clock frequency to its initial frequency in the predetermined order.

12. A method of associating a time value with specified events, the events stored in memory, comprising:

generating a clock signal from a range of clock frequencies;

generating in response to the clock signal a binary code count to be associated as a time value with each specified event;

selecting progressively slower clock frequencies as the code count changes;

signaling the occurrence of a specified event;

storing the binary code count associated with each specified event; and

resetting the clock frequency to its initial clock frequency each time a specified event occurs.

13. The method of claim 12 including reading the binary code count to select the clock frequency providing the clock signal and resetting the binary code count each time a specified event occurs to reset the clock frequency.

14. The method of claim 12 including warning that two specified events have occurred too close in time to generate binary output counts that validly reflect the time therebetween.

15. The method of claim 12 including comparing the binary code count of two events to determine the elapsed time between the events.