Gate-array chip

• US 4,733,288 A
• Filed: 02/10/1986
• Issued: 03/22/1988
• Est. Priority Date: 06/30/1982
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sato, Shinji
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): PRENTY, MARK V
• Application Number:
  US06/828,097
• Time in Patent Office: 771 Days
• Field of Search: 357/40, 357/45, 357/68
• US Class Current: 257/268
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/09425 Multistate logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/09429 one of the states being the high impedance or floating state
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks
• CPC Class Codes: H03K 5/023 using field effect transistors

Abstract

A gate-array chip includes a plurality of basic-cell arrays arranged in parallel on a semiconductor bulk and a plurality of impurity regions formed on the semiconductor bulk and in regions between the basic-cell arrays. The impurity regions and part of the basic-cell arrays are adapted to form input/output circuits whereby the gate-array chip is divided into several chips each having a desired size and a desired number of gates.

Claims

1. A gate-array chip comprising:

a semiconductor bulk;

a plurality of groups of basic-cell arrays arranged in parallel on said semiconductor bulk of said gate-array chip, each of said groups of basic-cell arrays including a plurality of basic-cells;

a plurality of impurity regions provided for each of said groups of basic-cell arrays, formed on said semiconductor bulk and in regions between each of said groups of basic-cell arrays, first predetermined ones of said impurity regions and first predetermined ones of said groups of basic-cell arrays located on either side of said predetermined ones of said impurity regions connected to form input/output circuits;

a first cutting region, formed between second predetermined ones of said basic-cell arrays, for enabling said plurality of groups of basic-cell arrays on said gate-array chip to be cut into smaller plurality of groups of basic cell arrays to form chips smaller than said gate-array chip; and

first input/output pad forming regions formed adjacent to said first cutting region.

2. A gate-array chip as set forth in claim 1, further comprising:

an insulating film formed on each of said plurality of impurity regions; and

a contact window selectively formed in said insulating film, each of said impurity regions being electrically connected, through said contact window, to at least one of said basic cells.

3. A gate-array chip as set forth in claim 2, further comprising an input/output circuit formed by a connection of one of said plurality of impurity regions and said at least one of said basic cells, said impurity region being electrically connected through said contact window to said at least one of said basic cells.

4. A gate-array chip as set forth in claim 3, further comprising a plurality of wiring regions, each of said plurality of wiring regions being provided between said basic-cell arrays, at least one of said wiring regions forming the first cutting region for cutting said gate-array chip into a plurality of chips.

5. A gate-array chip as set forth in claim 4, further comprising at least one second cutting region, formed on said plurality of basic cell arrays and extending in a direction orthogonal to the direction of said basic-cell arrays, for dividing said gate-array chip into a plurality of chips.

6. A gate-array chip as set forth in claim 5, further comprising a second input/output pad-forming region formed in said at least one second cutting region.

7. A gate-array chip as set forth in claim 6, wherein said input/output circuit is formed adjacent to one of said first input/output pad-forming region and said second input/output pad-forming region.

8. A gate array chip formed on a semiconductor bulk, comprising:

groups of basic-cell arrays, arranged in parallel on the semiconductor bulk, each of said groups of basic-cell arrays including basic-cells;

a first cutting region, formed on the semiconductor bulk and adjacent each of said groups of basic cell arrays, for cutting said groups of basic-cell arrays on said gate array chip in a first direction into a plurality of groups of basic-cell arrays which are smaller than said groups of basic-cell arrays, to form chips smaller than said gate array chips ;

wiring regions, formed on the semiconductor bulk and provided between adjacent ones of said groups of basic-cell arrays, at least a first one of said wiring regions formed adjacent said first cutting region for forming input/output pads, and at least a second of one of said wiring regions formed adjacent said first one of said wiring regions and formed between at least two of said groups of basic-cell arrays, said second one of said wiring regions and said at least two of said groups of basic-cell arrays being connected to form input/output circuits;

a second cutting region formed on the semiconductor bulk and extending in a second direction orthogonal to said first cutting region for cutting said plurality of groups of basic-cell arrays in the second direction into smaller groups of basic-cell arrays to form chips smaller than said gate array chip; and

impurity diffusion regions, formed under said wiring regions and between each of said groups of basic-cell arrays, said impurity diffusion regions and selected ones of said groups of basic-cells connected to form buffer circuits.

9. A gate array chip as set forth in claim 8, wherein said at least one of said wiring regions for forming said first cutting region is smaller in width than the remaining wiring regions.

10. A gate array chip as set forth in claim 9, wherein when said gate-array chip is cut into a plurality of chips, contact windows are selectively opened on said at least one of said wiring regions to form the input/output circuits.