Dynamic random access memory arrangements having WE, RAS, and CAS derived from a single system clock

• US 4,734,880 A
• Filed: 03/20/1984
• Issued: 03/29/1988
• Est. Priority Date: 04/12/1983
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Collins, Mark C.
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Chan, Emily Y.
• Application Number:
  US06/591,564
• Time in Patent Office: 1,470 Days
• Field of Search: 365/194, 365/189, 365/233, 364/900 MS File, 364/200 MS File, 364/200, 364/900
• US Class Current: 711/105
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence

Abstract

A dynamic random access memory arrangement for storing digital television signal data under control of a system clock signal CK and input address signals A0 to A17 associated with the data, has a dynamic random access memory having a data input and a data output for the data, and an address input for the input address signals, the dynamic random access memory being controlled by a write enable signal WE, a row address strobe signal RAS and a column address strobe signal CAS, and a logic circuit is provided to derive the signals WE, RAS and CAS from the system clock signal CK with respective timings each determined by a leading edge of a pulse of the system clock signal CK and delay devices.

Claims

1. A dynamic random access memory arrangement for storing digital television signal data under control of a single system clock signal from a system clock generator and input address signals corresponding to said data, the arrangement comprising:

delay means receiving said single system clock signal for producing therefrom a plurality of latch clock signals having predetermined time delays;

means for deriving a write enable signal, a row address strobe signal, and a column address strobe signal from said single system clock signal, wherein timing of each respective write enable signal, row address strobe signal, and column address strobe signal is determined by a leading edge of successive pulses of said single system clock signal; and

dynamic random access memory means having a data input and a data output for said data, and an address input for said input address signals; and

latch means connected to said address input, said data input, and said data output, of said dynamic random access memory means for controlling address and data flow therein in response to said plurality of latch clock signals, and said dynamic random access memory is controlled by said write enable signal, said row address strobe signals and said column address strobe signal, whereby said digital television signal data fed into said data input through said latch means is stored in said dynamic random access memory at addresses determined by said input address signals in response to said write enable signal, said row address strobe signal and said column address strobe signal.

2. An arrangement according to claim 1 wherein said delay means comprise a plurality of calibrated, series connected delay lines each producing a respective one of said latch clock signals from said single system clock signal and each latch clock signal having a respective predetermined time delay for feeding to said means for deriving.

3. An arrangement according to claim 1 wherein said means for deriving said write enable signal, said row address strobe signal, and said column address strobe signal is a circuit comprising a plurality of logic gates and a calibrated delay line.

4. An arrangement according to claim 2, wherein said delay means comprises first and second delay devices, said first delay device being connected to receive said system clock signal for producing a first delayed signal by delaying said system clock signal by a first predetermined amount, and said second delay device being connected to receive said first delayed signal for producing a second delayed signal by delaying said first delayed signal by a second predetermined amount, substantially less than said first predetermined amount.