Microprocessor controlled signal discrimination circuitry

• US 4,734,881 A
• Filed: 02/18/1986
• Issued: 03/29/1988
• Est. Priority Date: 02/18/1986
• Status: Expired due to Term

• Current Assignee: 3M Company
• Original Assignee: 3M Company
• Inventors: Klein, Theodore D., Oran, Michael R.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/830,535
• Time in Patent Office: 770 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/240
• CPC Class Codes: G08C 25/00 Arrangements for preventing or correcting errors; Monitoring arrangements
• CPC Class Codes: G08G 1/087 Override of traffic control, e.g. by signal transmitted by an emergency vehicle

Abstract

Circuitry for the validation of repetitive signals including input/output circuitry providing information regarding signals received that is connected to a progammable microprocessor, a read only memory and random access memory. The microprocessor is programmed so the circuitry determines the receipt of an input signal at any one of several signal inputs. When a first signal is received at one of the signal inputs a "lock-out" time interval is provided during which another signal cannot be received at any signal input. This is followed by a "window" time interval during which another input signal can be received at the signal input receiving the first signal. A "lock-out" and a "window" time interval are provided for each signal received at the signal input during a "window" time period at which the first input signal was received. Such signals are counted until a predetermined count is reached thereby establishing the received signals as valid signals. A new count is required is a "window" time interval is provided and a signal is not received at the proper input during such time interval.

Claims

1. Circuitry for the validation of repetitive signals received by the circuitry including:

input/output circuitry having a plurality of signal inputs for receiving signals, said input/output circuitry providing information as to when and which of said signal inputs receives a signal and is controlled by a microprocessor for establishing when and at which of said signal inputs a signal can be received;

programmable microprocessor connected to said input/output circuitry;

a random access memory connectd to said input/output circuitry and said programmable microprocessor;

a read only memory connected to said programmable microprocessor for storing instructions for said programmable microprocessor;

said programmable microprocessor programmed for operating with said input/output circuitry and said random access memory for controlling said input/output circuitry for permitting any of said signal inputs to receive a signal and when a signal is received at one of said signal inputs providing a "lock-out" time interval during which none of said signal inputs can receive a signal and upon completion of said lock-out time interval establishing a "window" time interval during which a signal can be received only at said one of said signal inputs, said "lock-out" and "window" time intervals being provided each time a signal is received at said one of said signal inputs permitting any of said signal inputs to receive a signal in the event a signal is not received during a "window" time interval, a signal received to establish said one of said signal inputs being considered valid by said programmable microprocessor when a predetermined number of signals are received at said one of said inputs before a "window" interval is provided during which a signal is not received at said one of said inputs.

2. Circuitry according to claim 1 wherein said programmable microprocessor is programmed with exits provided at various points.

3. Circuitry according to claim 1 wherein said input/output circuitry provides a pulse signal interrupt to said programmable microprocessor in response to a signal received at one of said signal inputs when any of said inputs are permitted to receive a signal which may or may not initiate operation of said programmable whether said signal received at said one signal input is valid.

4. Circuitry according to claim 1 wherein said programmable microprocessor is programmed for operating said input/output circuitry and said random access memory for providing a count of a signal received at one of said signal inputs when any of said signal inputs are permitted to receive a signal and subsequent signals received during a "window" time interval at said one signal input until a predetermined count is reached.

5. Circuitry according to claim 4 wherein said programmable microprocessor is programmed so that when said predetermined count is reached only an input signal received at said one signal input will cause said input/output circuitry to provide a pulse signal interrupt to said programmable microprocessor.