Versatile interconnection bus
First Claim
1. In a bus arbitration system comprising a bus which consists of a plurality of bus lines and a plurality of bus contention means coupled to said bus lines that are each capable of contending for control of said bus, the improvement comprising clock means for producing clock signals of at least first and second signal phases, wherein each of said bus contention means comprisedrive means coupled to each of said plurality of lines of said bus and constructed to unconditionally drive each line of said bus to a first logic state during said first clock signal phase in order to precharge the capacitance associated with said bus lines and to conditionally drive each of said bus lines to either a first logic state, or to a second logic state,, in accordance with an established priority code during said second clock signal phase,read means for reading the logic state of said bus lines during said second clock signal phase,priority determining means for comparing the logic state patterns of the bus lines which are associated with the priority codes of each of said bus contention means with the logic state pattern that is established by said conditionally driven lines and for removing all of said bus contention means from contention for said bus for which said logic state patterns do not match.
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Accused Products
Abstract
A bus arbitration system comprising a plurality of bus lines and a clock which produces first and second phrases in which a drive generates a first logic state during the first phase to precharge the capacitance associated with the bus lines and generates either first or second logic state during the second phase. Also, a bus interface is described in which different types of information are transmitted during different phases.
53 Citations
12 Claims
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1. In a bus arbitration system comprising a bus which consists of a plurality of bus lines and a plurality of bus contention means coupled to said bus lines that are each capable of contending for control of said bus, the improvement comprising clock means for producing clock signals of at least first and second signal phases, wherein each of said bus contention means comprise
drive means coupled to each of said plurality of lines of said bus and constructed to unconditionally drive each line of said bus to a first logic state during said first clock signal phase in order to precharge the capacitance associated with said bus lines and to conditionally drive each of said bus lines to either a first logic state, or to a second logic state,, in accordance with an established priority code during said second clock signal phase, read means for reading the logic state of said bus lines during said second clock signal phase, priority determining means for comparing the logic state patterns of the bus lines which are associated with the priority codes of each of said bus contention means with the logic state pattern that is established by said conditionally driven lines and for removing all of said bus contention means from contention for said bus for which said logic state patterns do not match.
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11. A bus interface having a fixed number of connecting pins comprising timing means that provides successive timing clock phases, first means comprising means for supplying first binary signals which are selectively representative of one or more of the following Group A types of coded information:
- (1) data, (2) address, or (3) function, a plurality of Group A interconnection pins, and means for selecting the number of said Group A pins which may receive said first binary signals representative of each type of Group A information during any given clock phase wherein the number of pins may vary from zero for each type of Group A information, to all of said Group A pins, and second means comprising means for supplying second binary signals which are selectively representative of one or more of the following Group B types of coded information;
(1) arbitration priority, (2) slave identification, (3) address, or (4) function, a plurality of Group B interconnection pins, and means for selecting the number of Group B pins which may receive said second binary signals representative of each type of Group B information during any given clock phase, wherein the number of pins may vary from zero to all of said Group B pins for each type of Group B information, and timing means for controlling the timing of said first and said second binary signals so that said first binary signals that are coupled to their selected Group B pins during a clock phase that succeeds the clock phase during which said second binary signals are coupled to their selected Group A pins. - View Dependent Claims (12)
- (1) data, (2) address, or (3) function, a plurality of Group A interconnection pins, and means for selecting the number of said Group A pins which may receive said first binary signals representative of each type of Group A information during any given clock phase wherein the number of pins may vary from zero for each type of Group A information, to all of said Group A pins, and second means comprising means for supplying second binary signals which are selectively representative of one or more of the following Group B types of coded information;
Specification