Semiconductor memory

• US 4,736,344 A
• Filed: 03/25/1986
• Issued: 04/05/1988
• Est. Priority Date: 03/25/1985
• Status: Expired due to Term

• Current Assignee: Lid Hitachi
• Original Assignee: Hitachi, Ltd.
• Inventors: Yanagisawa, Kazumasa
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/843,612
• Time in Patent Office: 742 Days
• Field of Search: 365/222, 365/230, 365/149, 365/189
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A refresh arrangement is provided for a dynamic RAM wherein each time a refresh address counter performs a predetermined plurality of steps of increment operations, an address switching circuit is switched to specified refresh addresses held in an address storage circuit to provide addresses of memory cells having inferior data retention times. In this way the memory cells with inferior data retention times can be refreshed much more frequently than memory cells with normal data retention times.

Claims

1. A semiconductor memory provided with a refresh control circuit for periodically refreshing memory cells of said semiconductor memory, wherein said refresh control circuit comprises:

an address counter circuit including means for performing a plurality of steps of increment operations to form refresh address signals for a first group of said memory cells;

an address storage circuit which stores specified refresh addresses for a second group of said memory cells; and

an address switching circuit coupled to said address counter circuit and said address storage circuit, said address switching circuit including means for outputting the refresh address signals from said address counter circuit during a predetermined plurality of said increment operations and for outputting the specified refresh addresses held in said address storage circuit each time said address counter has performed said predetermined plurality of steps of increment operations.

2. A semiconductor memory according to claim 1, wherein said address counter circuit comprises a first counter circuit including a divided-by-(2ⁿ +1) counter (where n is an integral number greater than or equal to 1) which receives an increment pulse, and a second counter circuit which receives an output signal of the most significant bit of said first counter circuit, wherein the refresh address signals are formed by output signals of respective bits of said first counter circuit, except the most significant bit thereof, and output signals of respective bits of said second counter circuit, and wherein a control signal to be supplied to said address switching circuit is formed on the basis of the output of the most significant bit of said first counter circuit.

3. A semiconductor memory according to claim 1, wherein said address storage circuit stores the specified refresh addresses by selectively cut fuse means.

4. A semiconductor memory comprising:

a plurality of memory cells;

first means for repeatedly refreshing memory cells of specified addresses in accordance with a first refresh period; and

second means for repeatedly refreshing memory cells except those to be refreshed with the first period in accordance with a second refresh period which is longer than the first refresh period.

5. A semiconductor memory according to claim 4, wherein the first means includes means for carrying out the refresh with the first refresh period a plurality of times in a time interval in which the refresh by the second means with the second refresh period is performed once.

6. A semiconductor memory including a plurality of memory cells arranged in an array, wherein a first group of said memory cells has data retention times less than a predetermined time, and wherein a second group of said memory cells has data retention times greater than said predetermined time period, wherein said semiconductor memory includes a refresh circuit comprising:

an address counter circuit including means for performing a plurality of steps of increment operation to form refresh address signals for said second group of memory cells so that each of said memory cells of said second group is refreshed in accordance with a first refresh period which is greater than said predetermined time period;

an address storage circuit which stores addresses of said first group of memory cells; and

an address switching circuit coupled to said address counter circuit and to said address storage circuit, said address switching circuit including means for outputting the refresh address signals from said address counter circuit during a predetermined plurality of steps of increment operation to refresh memory cells within said second group of memory cells and for outputting the stored addresses of said first group of memory cells each time said address counte circuit has performed said predetermined plurality of steps of increment operation so that said memory cells of said first group of memory cells are refreshed in accordance with a second refresh period which is shorter in time than said predetermined time period.

7. A semiconductor memtory including a plurality of memory cells arranged in an array, wherein each of said memory cells includes capacitor means for storing data, wherein a first group of said memory cells has a data retention time period which is less than a predetermined time period, and wherein a second group of said memory cells has a data retention time period which is greater than said predetermined time period, said semiconductor memory comprising:

row selecting means coupled to said array and responsive to address signals for selecting memory cells indicated by the address signals from said plurality of memory cells; and

a refresh circuit coupled to said row selecting means and for generating the address signals which indicate a memory cell to be refreshed, wherein said refresh circuit includes first refresh means for forming the address signals for said second group so that each of memory cells of said second group is refreshed in accordance with a first refresh period which is greater than said predetermined time period, and second refresh means for forming the address signals for said first group so that each of memory cells of said first group is refreshed in accordance with a second refresh period which is shorter in time than said predetermined period.

8. A semiconductor memory according to claim 7, wherein said second refresh means includes a storage circuit for storing address signals which indicate the memory cells of said first group and means for forming the address signals of said second refresh means on the basis of the stored address signals in said storage circuit.

9. A semiconductor memory according to claim 8, wherein said refresh circuit further includes switching means which receives the address signals of said first refresh means and the address signals of said second refresh means and outputs the address signals of said refresh circuit.

10. A semiconductor memory according to claim 9, further comprising an address circuit which generates input address signals, and a switching circuit which is coupled to said address circuit, to said refresh circuit and to said row selecting means, and which transfers either the input address signals or the address signals of said refresh circuit to said row selecting means.

11. A semiconductor memory according to claim 7, wherein said refresh circuit further includes switching means which receives the address signals of said first refresh means and the address signals of said second refresh means and outputs the address signals of said refresh circuit.

12. A semiconductor memory according to claim 11, further comprising an address circuit which generates input address signals, and a switching circuit which is coupled to said address circuit, to said refresh circuit and to said row selecting means, and which transfers either the input address signals or the address signals of said refresh circuit to said row selecting means.