Method and apparatus for controlling access to an asynchronous communication network

• US 4,736,365 A
• Filed: 10/26/1984
• Issued: 04/05/1988
• Est. Priority Date: 10/26/1984
• Status: Expired due to Fees

• Current Assignee: Dialogic Systems Corporation
• Original Assignee: Dialogic Systems Corporation
• Inventors: Stern, Richard M.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US06/665,416
• Time in Patent Office: 1,257 Days
• Field of Search: 370/85, 370/67, 370/24, 370/29, 370/84
• US Class Current: 370/276
• CPC Class Codes: G06F 11/16 Error detection or correction of the data by redundancy in hardware
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/36 for access to common bus or bus system

Abstract

A method and apparatus for communication circuit acquisition in an information processing system for high throughput communication of digital information is disclosed. High throughput is achieved by providing acquire logic circuitry for acquiring a communication circuit among a multiplicity of communication circuits, which are preferably four-wire, full duplex bidirectional channels for serial communication of digital information, and by preferably providing full duplex, bidirectional communication of messages at a first rate and half duplex, unidirectional communication of large blocks of data at a second higher rate over the communication circuits. The acquire logic circuitry frees the processor included in a communication controller associated with each information processing element to perform other data processing functions so that the processor is not burdened by monitoring the availability of the communication circuits for transmission of digital information. The method and apparatus facilitate circuit implementation of an architecture for high throughput fault tolerant serial communication of digital information in a loosely coupled information processing system. Other features are also disclosed.

Claims

1. A method for digital information communication whereby at least one of a plurality of information processing elements is coupled to at least one other of the plurality of information processing elements, comprisng the steps of:

interfacing each of the plurality of information processing elements to a plurality of coupling means connected to at lest one communication circuit;

interfacing each of a plurality of communication controller means associated with the plurality of coupling means to the communication circuit;

initiating communication circuit acquisition means included in the communication controller means in response to a control signal produced by a processor included in the communication controller means when access to the communication circuit is needed for communication of digital information from the one information processing element to another;

releasing the processor to perform other data processing functions;

detecting the availability of the communication circuit by means of the communication circuit acquisition means;

acquiring the communication circuit under control of the communication circuit acquisition means for transmission of digital information over the communication circuit;

maintaining availability of the communication circuit under control of the communication circuit acqusition means for transmission of digital information over the communication circuit; and

initiating transmission of digital information over the communication circuit acquired by the communication circuit acquisition means under control of the processor.

2. The method of claim 1, further comprising the steps of:

initiating the communication circuit acquisition means in response to a second control signal produced by the processor at the conclusion of transmission of digital information; and

releasing the communication circuit in response to the second control signal under control of the communication circuit acquisition means.

3. The method of claim 1, further comprising the steps of:

detecting an end of record flag included in the transmitted digital information by means of the communication circuit acquisition means; and

releasing the communication circuit in response to the end of record flag under control of the communication circuit acquisition means;

whereby the communication circuit acquisition means automatically releases the communication circuit.

4. The method of claim 1, further comprising the steps of:

exchanging digital information in the form of messages among the plurality of communication controller means under control of the plurality of communication controller means, at least certain of the messages exchanged among the plurality of communication controller means being for control of the exchange of digital information in the form of data among the plurality of coupling means for use by the plurality of information processing elements; and

connecting the plurality of coupling means and communication controller means to a plurality of four-wire, full duplex communication circuits for transferring digital information among the plurality of coupling means and communication controller means, respectively, in bit-serial format;

whereby high throughput fault tolerant digital information communication in serial format is provided.

5. The method of claim 4 wherein the exchange of messages comprises bidirectionally communicating digital information at a first rate and the exchange of data comprises unidirectionally communicating digital information at a second higher rate.

6. A method for digital information communication whereby at least one of a plurality of information processing elements is coupled to at least one other of the plurality of information processing elements, comprising the steps of:

interfacing each of the plurality of information processing elements to a plurality of coupling means connected to at least one communication circuit;

initiating communication circuit acquisition means included in communication controller means in response to a control signal produced by a processor included in the communication controller means when access to the communication circuit is needed for communication of digital information from the one information processing element to the other;

releasing the processor to perform other data processing functions;

monitoring the communication circuit by means of the communication circuit acquisition means;

detecting the availability of the communication circuit by means of the communication circuit acquisition means;

acquiring the communication circuit under control of the communication circuit acquisition means for transmission of digital information over the communication circuit;

maintaining availability of the communication circuit under control of the communication circuit acquisition means for transmission of digital information over the communication circuit;

interrupting the processor upon acquisition of the communication circuit in response to an interrupt signal produced by the communication circuit acquisition means; and

initiating transmission of digital information over the communication circuit acquired by the communication circuit acquisition means in response to the interrupt signal under control of the processor.

7. The method of claim 6, further comprising the steps of:

initiating the communication circuit acquisition means in response to a second control signal produced by the processor at the conclusion of transmission of digital information; and

releasing the communication circuit in response to the second control signal under control of the communication circuit acquisition means.

8. The method of claim 6, further comprising the steps of:

detecting an end of record flag included in the transmitted digital information by means of the communication circuit acquisition means; and

releasing the communication circuit in response to the end of record flag under control of the communication circuit acquisition means;

whereby the communication circuit acquisition means automatically releases the communication circuit.

9. The method of claim 6, further comprising the steps of:

exchanging digital information in the form of messages among the plurality of communication controller means under control of the plurality of communication controller means, at least certain of the messages exchanged among the plurality of communication controller means being for control of the exchange of digital information in the form of data among the plurality of coupling means for use by the plurlaity of information processing elements; and

connecting the plurality of coupling means and communication controlling means to a plurality of four-wire, full duplex communcation circuits for transferring digital information among the plurality of coupling means and communication controller means, respectively, in bit-serial format;

whereby high throughput fault tolerant digital information communication in serial format is provided.

10. The method of claim 9 wherein the exchange of messages comprises bidirectionally communicating digital information at a first rate and the exchange of data comprises unidirectionally communicating digital information at a second higher rate.

11. Apparatus for digital information communication whereby at least one of a plurality of information processing elements is coupled to at least one other of the plurality of information processing elements, comprising:

means for interfacing each of the plurality of information processing elements to a plurality of coupling means connected to a communication circuit;

means for interfacing each of a plurality of communication controller means associated with the plurality of coupling means to the communication circuit;

a processor included in the communication controller means for producing a control signal when access to the communication circuit is needed for communication of digital information from the one information processing element to another; and

communication circuit acquisition means included in the communication controller means responsive to the control signal for acquiring the communication circuit, the communication circuit acquisition means maintaining availability of the communication circuit for transmission of digital information over the communication circuit, thereby releasing the processor to perform other data processing functions;

the processor initiating transmission of digital information over the communication circuit acquired by the communication circuit acquisition means.

12. The apparatus of claim 11 wherein the processor produces a second control signal for initiating the communication circuit acquisition means at the conclusion of transmission of digital information and the communication circuit acquisition means is responsive to the second control signal for releasing the communication circuit.

13. The apparatus of claim 11 wherein the communication circuit acquisition means detects an end of record flag included in the transmitted digital information and releases the communication circuit in response to the end of record flag, whereby the communication circuit acquisition means automatically releases the communication circuit.

14. The apparatus of claim 11 wherein there is a plurality of four-wire, full duplex communication circuits, the plurality of coupling means interfaces each of the plurality of information processing elements to the plurality of communication circuits in order to exchange digital information in the form of data among the plurality of coupling means for use by the plurality of information processing elements, the plurality of communication controller means is connected to the plurality of coupling means for exchanging digital information in the form of messages among the plurality of communication controller means, at least certain of the messages exchanged among the plurality of communication controller means being for control of the exchange of data among the plurality of coupling means, and further comprising serial interface means for connecting the plurality of coupling means and communication controller means to the plurality of communication circuits for transferring digital information among the plurality of coupling means and communication controller means, respectively, in bit-serial format, thereby providing high throughput fault tolerant digital information communication in serial format.

15. The apparatus of claim 14 wherein the plurality of communication circuits forms a set of communication circuits for bidirectionally communicating digital information in the form of messages at a first rate and characterized in that a predetermined subset of the communication circuits is provided for unidirectionally communicating digital information in the form of data at a second higher rate.

16. Apparatus for digital information communication whereby at least one of a plurality of information processng elements is coupled to at least one other of the plurality of information processing elements, comprising:

means for interfacing each of the plurality of information processing elements to a plurality of coupling means connected to a communication circuit;

means for interfacing each of a plurality of communication controller means associated with the plurality of coupling means to the communication circuit;

a processor included in the communication controller means for producing a control signal when access to the communication circuit is needed for communication of digital information from the one information processing element to another;

communication circuit acquisition means included in the communication controller means responsive to the control signal for acquiring the communication circuit, the communication circuit acquisition means maintaining availability of the communication circuit for transmission of digital information over the communication circuit, thereby releasing the processor to perform other data processing functions;

the communication circuit producing an interrupt signal when the communication circuit is acquired by the communication circuit acquisition means; and

the processor being responsive to the interrupt signal for initiating transmission of digital information over the communication circuit acquired by the communication circuit acquisition means.

17. The apparatus of claim 16 wherein the processor produces a second control signal for initiating the communication circuit acquisition means at the conclusion of transmission of digital information and the communication circuit acquisition means is responsive to the second control signal for releasing the communication circuit.

18. The apparatus of claim 16 wherein the communication circuit acquisition means detects an end of record flag included in the transmitted digital information and releases the communication circuit in response to the end of record flag, whereby the communication circuit acquisition means automatically releases the communication circuit.

19. The apparatus of claim 16 wherein there is a plurality of four-wire, full duplex communication circuits, the plurality of coupling means interfaces each of the plurality of information processing elements to the plurality of communication circuits in order to exchange digital information in the form of data among the plurality of coupling means for use by the plurality of information processing elements, the plurality of communication controller means is connected to the plurality of coupling means for exchanging digital information in the form of messages among the plurality of communication controller means, at least certain of the messages exchanged among the plurality of communication controller means being for control of the exchange of data among the plurality of coupling means, and further comprising serial interface means for connecting the plurality of coupling means and communication controller means to the plurality of communication circuits for transferring digital information among the plurality of coupling means and communication controller means, respectively, in bit-serial format, thereby providing high throughput fault tolerant digital information communication in serial format.

20. The apparatus of claim 19 wherein the plurality of communication circuits forms a set of communication circuits for bidirectionally communicating digital information in the form of messages at a first rate and characterized in that a predetermined subset of the communication circuits is provided for unidirectionally communicating digital information in the form of data at a second higher rate.

21. A digital information communication network whereby at least one of a plurality of information processing elements is loosely coupled to at least one other of the plurality of information processing elements, comprising:

a plurality m of four-wire, full duplex communication channels;

a plurality n of personality module circuits connected to the plurality of information processing elements and a preselected subset of the m communication channels for interfacing the plurality of information processing elements to the preselected subset of the m communication channels in order to exchange digital information in the form of data among the n personality module circuits, each one of the n personality module circuits including a first serial interface comprising;

(a) a first direct memory access interface in series with

(b) a first serial interface circuit in series with

(c) a first multiplexer circuit;

the first serial interface for connecting the associated personality module circuit to the preselected subset of the m communication channels; and

a plurality n of system module circuits connected to the m communication channels and the n personality module circuits for exchanging digital information in the form of messages among the n system module circuits, at least certain of the messages exchanged among the n system module circuits being for control of the exchange of data among the n personality module circuits, each one of the n system module circuits including at least a second serial interface comprising;

(a) a second direct memory access interface in series with

(b) a second serial interface circuit in series with

(c) a second multiplexer circuit including acquire logic circuitry for acquiring one of the m communication channels;

the second serial interface for connecting the associated system module circuit to the m communication channels;

the data and messages being exchanged among the n personality module circuits and n system module circuits, respectively, in bit-serial format;

thereby providing high throughput fault tolerant digital information communication in serial format.

22. The apparatus of claim 21 wherein the m communication circuits form a set of communication circuits for bidirectionally communicating digital information in the form of messages at a first rate and characterized in that a predetermined subset of the m communication circuits is provided for unidirectionally communicating digital information in the form of data at a second higher rate.