Cache memory address apparatus

• US 4,737,909 A
• Filed: 04/01/1985
• Issued: 04/12/1988
• Est. Priority Date: 04/01/1985
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Harada, Edward
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US06/718,578
• Time in Patent Office: 1,107 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/3
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Abstract

In a processor system with a virtual memory organization and a cache memory table storing the physical addresses corresponding to the most-recenty used virtual addresses, access to the cache table is enhanced by associating upper and lower MSB portions of a virtual address with corresponding upper and lower portions of an associated cache address. The separate cache address portions are placed in separate cache address storage devices. Each cache address storage device is addressed by respective virtual address MSB portions. A physical address storage device stores physical addresses translated from virtual addresses in storage locations addressed by cache addresses associated with the respective virtual addresses from which the physical addresses were translated.

Claims

1. A cache memory address apparatus for use in a processing system producing virtual addresses, cache addresses corresponding to respective virtual addresses, and physical addresses translated from said virtual addresses, said apparatus comprising:

cache address storage means for storing a first portion of a cache address at a first cache address storage location that is addressed by a first portion of a virtual address to which said cache address corresponds and for storing a second portion of said cache address at a second cache address storage location that is addressed by a second portion of said virtual address;

gate means responsive to information stored in said cache address storage locations for providing a miss signal when either one of said cache address storage locations addressed by said virtual address does not contain a corresponding cache address portion which corresponds to said portion of said virtual address and for providing an enabling signal when said first and second cache address storage locations addressed by said virtual address contain first and second cache address portions which correspond, respectively, to said first and second portions of said virtual address; and

physical address storage means having a plurality of addressable storage locations for storing physical address portions at locations addressed by cache addresses formed from cache address portions stored in said cache address storage means and for providing, in response to said enabling signal, a physical address portion stored at a location addressed by said cache address.

2. The apparatus of claim 1 wherein said cache address storage means includes a pair of RAM'"'"'s each addressed by a respective portion of said virtual address.

3. The apparatus of claim 1 wherein each cache address storage location includes storage capability for storing, in addition to a cache address portion, flag data indicating the presence of absence of a cache address portion in said cache address storage location.

4. The apparatus of claim 3 wherein said processing system further includes means for entering said flag data into a cache address storage location at a predetermined place in said storage location.

5. The apparatus of claim 4 wherein said gate means comprises a NAND gate connected to receive flag data from both cache address storage locations addressed by said virtual address.

6. The apparatus of claim 2 wherein said processing system includes means for entering, for said virtual address, each of the first and second portions of said corresponding cache address into a respective one of said RAM'"'"'s at a cache address storage location addressed by said first and second portions, respectively, of said virtual address and for entering, at said first and second cache address storage locations, flag data indicating whether said first and second portions of said corresponding cache address have been entered, and said gate means is responsive to said flag data in said first and second cache address storage locations to provide said miss or said enabling signal.

7. A method for storing physical addresses in a system producing virtual addresses, cache addresses corresponding to respective virtual addresses, and physical addresses translated from said virtual addresses, comprising the steps of:

storing, for a virtual address, first and second portions of a corresponding cache address at first and second cache address storage location, respectively, addressed by first and second portions, respectively, of said virtual address;

entering, at said first and second cache address storage location, flag data indicating said storage;

determining based upon the presence or absence of flag data, whether said first and second cache address storage locations addressed by said first and second portions of said virtual address contain first and second cache address portions;

storing, at a physical address storage location addressed by said stored cache address, a physical address portion translated form said virtual address; and

if said first and second cache address storage location addressed by said portions of said virtual address are determined to contain first and second cache address portions, retrieving the physical address portion stored at said physical address location.