Remote monitoring system receiver with dual baud rate selector

• US 4,737,967 A
• Filed: 01/28/1987
• Issued: 04/12/1988
• Est. Priority Date: 01/28/1987
• Status: Expired due to Fees

• Current Assignee: Hazeltine Corporation (BAE Systems Plc)
• Original Assignee: Hazeltine Corporation (BAE Systems Plc)
• Inventors: Cahalan, Irving W.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Huseman, Marianne
• Application Number:
  US07/007,558
• Time in Patent Office: 440 Days
• Field of Search: 375/8-10, 375/122, 375/121, 370/84, 370/118, 340/825.06, 340/825.17, 340/310 A, 379/97, 379/98
• US Class Current: 375/223
• CPC Class Codes: H04L 5/02 Channels characterised by the type of signal
• CPC Class Codes: H04L 5/1446 of transmission speed
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A remote monitoring system (RMS) receiver which operates at a dual baud rate. The operating rate is selected to be the same as the rate being used by remote equipment originating the data link with the receiver. A modem associated with the receiver provides an indicator signal indicating phase shift keying (a high baud rate) or frequency shift keying (a low baud rate) is being received from the remote equipment. The indicator signal is used to select the baud rate of a programmable baud rate generator of the RMS receiver. This controls the baud rate signal which is supplied to an asynchronous interface controlling data transfer between the receiver and the modem.

Claims

1. An apparatus comprising:

(a) a remote monitoring system receiver including;

(i) a processor having an input/output for receiving and transmitting data;

(ii) a clock for generating a clock signal; and

(iii) a baud rate generator receiving the clock signal and generating a high baud rate clock signal and a low baud rate clock signal;

(b) modem means for selectively receiving/transmitting data at the high baud rate and at the low baud rate, said modem means having an indicator means for detecting receipt of a nigh baud rate signal and providing a high indicator signal in response thereto and for detecting receipt of a low baud rate signal and providing a low indicator signal in response thereto;

(c) switch means having a first input port receiving the high baud rate clock signal, a second input port receiving the low baud rate clock signal, a control input receiving the high indicator signal and the low indicator signal, and an output port providing the high baud rate clock signal in response to receipt by the control input of the high indicator signal, said output port providing the low baud rate clock signal in response to receipt by the control input of the low indicator signal; and

(d) storage register means having a first data port connected to the input/output of the processor, a second data port connected to the modem means and a clock port connected to the output port of the switch means, said storage register means for receiving, storing and transmitting data between said processor and said modem means in response to the baud rate signal provided by the output port of the switch means.

2. The apparatus of claim 1 wherein said switch means comprises a single pole, double throw switch responsive to said indicator signal.

3. The apparatus of claim 1 wherein said switch means comprises:

(a) a level shift circuit having an input connected to the output of said indicator means for receiving the indicator signal;

(b) a first NOR gate having inputs connected to the level shift circuit output and having and output;

(c) a first AND gate having one input connected to the baud rate ganerator for receiving the high baud rate clock signal, having another input connected to the first NOR gate output and having an output;

(d) a second AND gate having one input connected to the baud rate generator for receiving the low baud rate clock signal, having another input connected to the output of the level shift circuit and having an output; and

(e) a second NOR gate having one input connected to the first AND gate output, having another input connected to the second AND gate output and having an output port providing the high baud rate clock signal in response to receipt by the level shift circuit of the high indicator signal and providing the low baud rate clock signal in response to receipt by the level shift circuit of the low indicator signal.

4. The apparatus of claim 3 wherein said indicator means comprises:

(a) means for detecting receipt of a frequency shift keyed signal and providing the low indicator signal in response thereto; and

(b) means for detecting receipt of a phase shift keyed signal and providing the high indicator signal in response thereto.

5. The apparatus of claim 1 wherein said storage register means comprises an asynchronous communication interface adapter.

6. The apparatus of claim 1 wherein said receiver is associated with the secondary of a power distribution network.

7. The apparatus of claim 1 wherein said indicator means comprises:

(a) means for detecting receipt of a frequency shift keyed signal and providing the low indicator signal in response thereto; and

(b) means for detecting receipt of a phase shift keyed signal and providing the high indicator signal in response thereto.