Serial data bus for serial communication interface (SCI), serial peripheral interface (SPI) and buffered SPI modes of operation

• US 4,739,323 A
• Filed: 05/22/1986
• Issued: 04/19/1988
• Est. Priority Date: 05/22/1986
• Status: Expired due to Term

• Current Assignee: Continental Automotive GmbH (Continental AG)
• Original Assignee: Chrysler Corporation (Stellantis NV)
• Inventors: Fassnacht, Ronald E., Nasiadka, Jerry M., McCambridge, John M., Miesterfeld, Frederick O. R.
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US06/866,629
• Time in Patent Office: 698 Days
• Field of Search: 340/825.8, 340/825.51, 370/85
• US Class Current: 370/447
• CPC Class Codes: F02D 41/266 the computer being backed-up or assisted by another circuit, e.g. analogue
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4213 with asynchronous protocol
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle

Abstract

The aim of the Chrysler Collision Detector (CCD) Bus System is to allow multiple microprocessors to easily communicate with each other over a common pair of wires (called a bus) using a scheme similar to a telephone party line. All microprocessors connected to the bus are able to receive all messages transmitted on the bus. Any microprocessor with a message to transmit on the bus waits until any current user is finished before attempting to use it. Whenever the bus is available, its use is allocated on a first-come, first serve basis (i.e., whichever microprocessor first begins transmitting its message on the bus after any previous message finishes gets the use of the bus). If, however, multiple microprocessors attempt to begin transmitting their messages on the bus at exactly the same time, then the message with the highest priority wins the use of the bus. All messages have unique message priority values and each message is transmitted by only one microprocessor. The subject invention provides the ability to communicate with a SCI port, a SPI port or a buffered SPI port. This allows communication with any device configured with any one of these ports, all on the same bus.

Claims

1. A communication system for the transmission of data messages through a data bus between two or more user microprocessors coupled to the data bus, the user microprocessors having any one of the following interface ports;

a serial communications interface (SCI) port, a serial peripheral interface (SPI) port or a buffered serial peripheral interface (BSPI) port along with a clock port and an input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, the bus interface integrated circuit comprising;

a reset circuit;

an arbitration detector;

a buffer;

a collision detector;

a bus driver;

a bus receiver;

an idle detector;

a series circuit formed by the connection of the arbitration detector, collision detector and bus driver connected between the interface port of the user microprocessor and the data bus to transmit data from the user microprocessor to the data bus;

the bus receiver connected between the data bus and the interface port of the user microprocessor to receive data messages from the data bus to the user microprocessor;

the idle detector comprising an idle counter and idle flip-flop connected betwen the input/output port of the user microprocessor and individually to the arbitration detector and collision detector to monitor the data bus and detect when the data bus is idle and when the data bus is busy;

a digital filter connected between the bus receiver and the SCI Port of the user microprocessor to filter out noise from the data messages before being processed by other parts of the bus interface integrated circuit;

timing and synchronizing means to establish synchronizing and a baud rate timing signal for use by the arbitration detector, collision detector and idle detector comprising;

a start/stop bit generator to generate start and stop bits;

a clock divider to receive a clock pulse from the user microprocessor to generate a clock signal;

a word counter to accept the clock signal and present timing and synchronizing information to the arbitration detector and to the collision detector;

a start bit detector to count and indicate when a start bit signal and level is present on the data bus;

a framing error detector to indicate when the stop bit level is not on the data bus at stop bit time;

the idle detector to monitor and indicate when the data bus is in an idle condition;

the bus interface integrated circuit being able to receive data from a user microprocessor configured for data communications in SCI, SPI or BSPI modes the bus interface integrated circuit further comprising;

a mode select circuit for controlling data and shift clock (SCK) signal flow into and out of the bus interface integrated circuit by responding to the particular interface of the user microprocessor and operating in accordance with that interface, SCI, SPI or BSPI;

an SCK selector for directing data in the buffered SPI mode and for describing the source of the clock signal for the buffer;

an SCK counter to count SCK pulses from the user microprocessor;

a byte counter for counting the number of bytes received;

an SPI clock generator to generate SCK pulses to the user microprocessor and buffer;

an SPI transmit scheduler and controller to control when data from a user microprocessor is put onto the bus in the SPI or BSPI modes; and

a current source and a current sink to drive the logical condition of the bus in response to signals from the bus driver and the bus receiver of the bus interface integrated circuit associated with each user microprocessor on the bus.

2. The bus interface integrated circuit of claim 1 further comprising:

a break generator to allow a user microprocessor to force a logical condition onto the bus.

3. The bus interface integrated circuit of claim 1 further comprising:

an over range latch and over range detector to detect when the voltage on the bus deviates from a predetermined voltage window and to indicate the deviation when it occurs.

4. The bus interface integrated circuit of claim 3 further comprising:

a test mode detector to signal the mode select circuit to pass data from the over range latch to the user microprocessor and to allow the user microprocessor to call for a reset.

5. A communication system for the transmission of data messages through a data bus between two or more user microprocessors coupled to the data bus, the user microprocessors having an interface port of the types:

a serial communications interface (SCI) port or a serial peripheral interface (SPI) port along with a clock port and an input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, the bus interface integrated circuit comprising;

an arbitration detector;

a collision detector;

a start/stop/shift clock (SCK) generator;

a bus driver;

a bus receiver;

and an idle and control detector;

a series circuit formed by the connection of the start/stop/SCK generator, the arbitration detector, collision detector and bus driver connected between the interface port of the user microprocessor and the data bus to transmit data from the user microprocessor to the data bus;

the bus receiver connected between the data bus and the interface port of the user microprocessor to receive data messages from the data bus to the user microprocessor;

the idle and control detector connected between the input/output port of the user microprocessor and individually to the arbitration detector and collision detector to monitor the data bus and detect when the data bus is idle and when the data bus is busy.

6. The bus interface integrated circuit of claim 5 further comprising:

a digital filter connected between the bus receiver and the SCI port of the user microprocessor to filter out noise from the data messages before being processed by other parts of the bus interface integrated circuit;

timing and synchronizing means to establish synchronizing and a baud rate timing signal for use by the arbitration detector, collision detector and idle detector comprising;

a clock divider to receive a clock pulse from the user microprocessor to generate a clock signal;

a word counter to accept the clock signal and present timing and synchronizing information to the arbitration detector and to the collision detector;

a start bit detector to indicate when a start bit signal and level is present on the data bus;

a framing error detector to indicate when the stop bit level is not on the data bus at stop bit time;

an idle detector to monitor and indicate when the data bus is in an idle condition.

7. A communication system for the transmission of data messages through a data bus between two or more user microprocessors coupled to the data bus, the user microprocessors having an interface port of the types:

a serial communications interface (SCI) port, a serial peripheral interface (SPI) port or a BSPI port along with a clock port and an input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, the bus interface integrated circuit comprising;

an arbitration detector;

a collision detector;

a start/stop/SCK generator;

a bus driver;

a bus receiver;

a buffer;

and an idle and control detector;

a series circuit formed by the connection of the buffer, the start/stop/SCK generator, the arbitration detector, collision detector and bus driver connected between the interface port of the user microprocessor and the data bus to transmit data from the user microprocessor to the data bus;

the bus receiver connected between the data bus and the interface port of the user microprocessor to receive data messages from the data bus to the user microprocessor;

the idle and control detector connected between the input/output port of the user microprocessor and individually to the arbitration detector and collision detector to monitor the data bus and detect when the data bus is idle and when the data bus is busy.

8. The bus interface integrated circuit of claim 7 further comprising:

a digital filter connected between the bus receiver and the SCI port of the user microprocessor to filter out noise from the data messages before being processed by other parts of the bus interface integrated circuit;

timing and synchronizing means to establish synchronizing and a baud rate timing signal for use by the arbitration detector, collision detector and idle detector comprising;

a clock divider to receive a clock pulse from the user microprocessor to generate a clock signal;

a word counter to accept the clock signal and present timing and synchronizing information to the arbitration detector and to the collision detector;

a start bit detector to indicate when a start bit signal and level is present on the data bus;

a framing error detector to indicate when a stop level is not on the data bus at stop bit time;

an idle detector to monitor and indicate when the data bus is in an idle condition.