Clock signal generating circuit for dynamic type semiconductor memory device
First Claim
1. A clock signal generating circuit for a dynamic type semiconductor memory device comprising:
- an input voltage level control means for converting a transistor-transistor-logic (TTL) drive level to a metal-oxide-semiconductor (MOS) drive level during transmission of an address strobe signal,an address buffer control means for generating an address signal and an inverted address signal in response to a trailing edge of the address strobe signal,a clock signal generating means for generating a clock signal used for a word line selection and an input signal for a next stage in response to a low level of the address strobe signal, andan inhibiting means for inhibiting a drive of the word line by the clock signal when the address strobe signal is at high level in the timing of a leading edge of the clock signal.
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Abstract
A clock signal generating circuit for a dynamic type semiconductor memory device including an input voltage level control unit for converting a transistor-transistor-logic (TTL) drive level to a metal-oxide-semiconductor (MOS) drive level during transmission of an address strobe signal; an address buffer control unit for generating an address signal and an inverted address signal in response to a trailing edge of the address strobe signal, a clock signal generating unit for generating a clock signal used for a word line selection and an input signal for a next stage in response to a low level of the address strobe signal, and an inhibiting unit for inhibiting a drive of the word line by the clock signal when the address strobe signal is at high level in the timing of a leading edge of the clock signal.
29 Citations
6 Claims
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1. A clock signal generating circuit for a dynamic type semiconductor memory device comprising:
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an input voltage level control means for converting a transistor-transistor-logic (TTL) drive level to a metal-oxide-semiconductor (MOS) drive level during transmission of an address strobe signal, an address buffer control means for generating an address signal and an inverted address signal in response to a trailing edge of the address strobe signal, a clock signal generating means for generating a clock signal used for a word line selection and an input signal for a next stage in response to a low level of the address strobe signal, and an inhibiting means for inhibiting a drive of the word line by the clock signal when the address strobe signal is at high level in the timing of a leading edge of the clock signal. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification