Switching device with dynamic hysteresis

• US 4,740,717 A
• Filed: 11/25/1986
• Issued: 04/26/1988
• Est. Priority Date: 11/25/1986
• Status: Expired due to Term

• Current Assignee: Signetics Corporation
• Original Assignee: North American Philips Corporation Signetics Division (Koninklijke Philips N.V.)
• Inventors: Shin, Yong-In, Fletcher, Thomas D.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US06/934,753
• Time in Patent Office: 518 Days
• Field of Search: 307/270, 307/273, 307/200 B, 307/451, 307/469, 307/491, 307/501, 307/443, 307/572, 307/290
• US Class Current: 326/24
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A switching device (22) responsive to an input voltage V_A is powered by low and high internal supply voltages V_L and V_H. The device changes state as V_A -V_L passes a threshold voltage V_T. After the device makes a desired change of state in response to rising V_A, a hysteresis circuit (24) temporarily decreases V_T below that which would otherwise be present. Likewise, after the device makes a desired change of state in the opposite direction when V_A is falling, the hysteresis circuit temporarily decreases V_T. In both cases, V_T later automatically returns to its original value. This dynamic hysteresis prevents spikes in V_L and V_H from causing undesired changes in state.

Claims

1. An electronic circuit in which a switching device responsive to an input voltage V_A is powered by (1) a low internal supply voltage V_L provided on a supply line coupled to a supply terminal for receiving an external supply voltage V_LL and (2) a high internal supply voltage V_H provided on a supply line coupled to a supply terminal for receiving an external supply voltage V_HH that exceeds V_LL by a largely constant amount, the device changing state as V_A -V_L passes a threshold voltage V_T such that, with V_T substantially at a value V_S and with V_L and V_H substantially at V_LL and V_HH, respectively, the device switches (1) from a first state to a second state as V_A rises above V_LL +V_S and (2) from the second state to the first state as V_A drops below V_LL +V_S, characterized by dynamic hysteresis means for performing at least one of (1) after V_A rises above V_LL +V_S, temporarily decreasing V_T below that which would be present in the absence of the means and (2) after V_A drops below V_LL +V_S temporarily increasing V_T above that which would be present in the absence of the means.

2. A circuit as in claim 1 characterized in that V_T returns to V_S before V_A starts moving in a direction opposite to the direction in which V_A was moving when V_T changed.

3. A circuit as in claim 1 wherein the device comprises a pair of input N-channel and P-channel field-effect transistors (FET'"'"'s) having respective gates responsive to V_A, respective sources coupled respectively to the V_L and V_H supply lines and respective drains coupled together to provide an output voltage V_B inverse to V_A, characterized in that the means controls V_T in response to V_B.

4. A circuit as in claim 3 in which there are a pair of output N-channel and P-channel FET'"'"'s having respective gates responsive to a voltage derived from at least V_B, respective sources coupled respectively to the V_L and V_H supply lines, and respective drains coupled together, the circuit being part of an integrated circuit having externally accessible terminals comprising an input terminal coupled to the gate of at least one of the input FET'"'"'s, an output terminal coupled to the drains of the output FET'"'"'s, and the supply terminals, characterized in that the means substantially prevents current flowing through the output terminal due to a change in V_B resulting from a change in V_A from causing V_B to change again.

5. An electronic circuit as in claim 1 wherein the device comprises first and second input conduction channels of opposite conductivity type, the first channel is coupled between the V_L supply line and a node, the second channel is coupled between the V_H supply line and the node, and each of the input channels turns on when the other turns off and vice versa, characterized in that the hysteresis means comprises:

at least one further conduction channel, each associated with one of the input channels, being of the same conductivity type as the associated input channel, and coupled between the node and the particular supply line coupled to the associated input channel; and

control means for causing each further channel to turn on temporarily when its associated input channel turns on.

6. A circuit as in claim 5 wherein each input channel is part of an input field-effect transistor (FET) having a gate electrode responsive to V_A, characterized in that each further channel is part of a further FET having a gate electrode responsive to a threshold-control voltage that controls the conduction of that further channel.

7. A circuit as in claim 6 wherein the node provides a voltage V_B inverse to V_A, characterized in that the control means comprises:

an inverter for providing a voltage V_E inverse to V_B ; and

charging/discharging means responsive to V_E for generating each threshold-control voltage.

8. An electronic circuit in which a switching device powered by a low supply voltage V_L and a high supply voltage V_H comprises a pair of input enhancement-mode N-channel and P-channel field-effect transistors (FET'"'"'s) having respective gates responsive to an input voltage V_A, respective sources respectively coupled to respective supply lines at voltages V_L and V_H, and respective drains coupled together to provide an output voltage V_B inverse to V_A, V_B changing in value as V_A -V_L passes a threshold voltage V_T such that, with V_T substantially at a value V_S and with V_L and V_H at respective values V_LL and V_HH, V_B switches (1) from a high voltage level to a low voltage level as V_A rises above V_LL +V_S and (2) from the low level to the high level as V_A drops below V_LL +V_S, characterized by dynamic hysteresis means for (1) after V_A rises above V_LL +V_S, temporarily decreasing V_T below that which would be present in the absence of the hysteresis means and (2) after V_A drops below V_LL +V_S, temporarily increasing V_T above that which would be present in the absence of the hysteresis means.

9. A circuit as in claim 8 characterized in that the hysteresis means comprises:

a pair of further enhancement-mode N-channel and P-channel FET'"'"'s having respective gates, respective sources coupled respectively to the V_L and V_H supply lines, and respective drains coupled to the drains of the input FET'"'"'s; and

control means for (1) causing the further N-channel FET to turn on temporarily in response to V_B going from the high level to the low level and (2) for causing the further P-channel FET to turn on temporarily in response to V_B going from the low level to the high level.

10. A circuit as in claim 9 characterized in that the control means provides (1) a first threshold-control voltage to the gate of the further N-channel FET and (2) a second threshold-control voltage to the gate of the further P-channel FET.

11. A circuit as in claim 8 characterized in that the hysteresis means comprises:

a pair of further enhancement-mode N-channel and P-channel FET'"'"'s having respective gates, respective sources coupled respectively to the V_L and V_H supply lines, and respective drains coupled to the drains of the input FET'"'"'s; and

control means (1) responsive to V_B going from the high level to the low level for charging the gate of the further N-channel FET to voltage sufficient to turn it on and later discharging the gate of the further N-channel FET to turn it off and (2) responsive to V_B going from the low level to the high level for charging the gate of the further P-channel FET to voltage sufficient to turn it on and later discharging the gate of the further P-channel FET to turn it off.

12. A circuit as in claim 11 characterized in that the control means comprises:

a pair of charge-supply enhancement-mode N-channel and P-channel FET'"'"'s having respective gates responsive to V_B, respective sources coupled respectively to the V_L and V_H supply lines, and respective drains coupled together for providing a voltage V_E inverse to V_B ;

first and second charging elements coupled to the drains of the charge-supply FET'"'"'s for providing charge respectively to the gates of the further N-channel and P-channel FET'"'"'s;

a first discharge element for providing a discharge path from the gate of the further N-channel FET to the V_L supply line; and

a second discharge element for providing a discharge path from the gate of the further P-channel FET to the V_H supply line.

13. A circuit as in claim 12 characterized in that (1) the first charging element temporarily provides charge to the gate of the further N-channel FET at a faster rate than that at which charge flows through the first discharge element to the V_L supply line and (2) the second charging element temporarily provides charge to the gate of the further P-channel FET at a faster rate than that at which charge flows through the second discharge element to the V_H supply line.

14. A circuit as in claim 13 characterized in that each charging element is a capacitive element.

15. A circuit as in claim 12 characterized in that the control means (1) activates the first charging element to charge the gate of the further N-channel FET before activating the first discharge element to discharge the gate of the further N-channel FET and (2) activates the second charging element to charge the gate of the further P-channel FET before activating the second discharge element to discharge the gate of the further P-channel FET.

16. A circuit as in claim 12 characterized in that:

the first charging element comprises a first inverter for producing a voltage V_F inverse to V_E, a second inverter for producing a voltage V_G inverse to V_F, and a pair of enhancement-mode N-channel and P-channel FET'"'"'s having respective gates respectively responsive to V_F and V_G, respective first source/drain elements coupled to the drains of the charge-supply FET'"'"'s, and respective second source-drain elements coupled to the gate of the further N-channel FET; and

the second charging element comprises the first inverter, the second inverter, and a pair of enhancement-mode N-channel and P-channel FET'"'"'s having respective gates respectively responsive to V_G and V_F, respective first source/drain elements coupled to the drains of the charge-supply FET'"'"'s, and respective second source-drain elements coupled to the gate of the further P-channel FET.

17. A circuit as in claim 16 characterized in that;

the first discharge element comprises an N-channel FET having a gate responsive to V_G, a source coupled to the V_L supply line, and a drain coupled to the gate of the further N-channel FET; and

the second discharge element comprises a P-channel FET having a gate responsive to V_G, a source coupled to the V_H supply line, and a drain coupled to the gate of the further P-channel FET.

18. A circuit as in claim 11 in which there are a pair of output enhancement-mode N-channel and P-channel FET'"'"'s having gates responsive to a voltage derived from at least V_B, respective sources coupled respectively to the V_L and V_H supply lines, and respective drains coupled together, characterized in that the FET'"'"'s and the hysteresis means are part of an integrated circuit having externally accessible terminals comprising an input terminal coupled to the gate of at least one of the input FET'"'"'s, an output terminal coupled to the drains of the output FET'"'"'s, and a pair of supply terminals respectively coupled to the V_L and V_H supply lines.

19. A circuit as in claim 18 characterized in that the hysteresis means substantially inhibits current flowing through the output terminal due to a change in V_B resulting from a change in V_A from causing V_B to change again.

20. An electronic circuit in which a switching device powered by a low supply voltage V_L and a high supply voltage V_H comprises a pair of input N-channel and P-channel field-effect transistors (FET'"'"'s) having respective gates responsive to an input voltage V_A, respective sources respectively coupled to respective supply lines at voltages V_L and V_H, and respective drains coupled together to provide an output voltage V_B inverse to V_A, V_B switching (1) from a high voltage level to a low voltage level as V_A -V_L rises above a threshold voltage V_T and (2) from the low level to the high level as V_A -V_L drops below V_T, characterized by dynamic hysteresis means comprising:

a pair of further N-channel and P-channel FET'"'"'s having respective gates, respective sources coupled respectively to the V_L and V_H supply lines, and respective drains coupled to the drains of the input FET'"'"'s; and

control means for (1) causing the further N-channel FET to turn on temporarily in response to V_B going from the high level to the low level and (2) for causing the further P-channel FET to turn on temporarily in response to V_B going from the low level to the high level.