Semiconductor memory device having a read-modify-write configuration

• US 4,740,922 A
• Filed: 10/17/1985
• Issued: 04/26/1988
• Est. Priority Date: 10/23/1984
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ogawa, Junji
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/788,398
• Time in Patent Office: 922 Days
• Field of Search: 365/189, 365/230, 365/238, 364/200
• US Class Current: 365/189.04
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

A semiconductor memory device having a read-modify-write (RMW) configuration suitable for modifying a large number of data with high speed and a simple circuit. The RMW configuration includes a data input and output circuit (11, 14, 16) for simultaneously storing or reading a plurality of data into or from the memory cells, a data output circuit (10, 12, 13) for serially reading a plurality of data from the memory cells, and data modification circuits (15) for successively receiving the plurality of data from the data output circuit, modifying the received data if necessary and transmitting the modified data to the data input and output circuit.

Claims

1. A semiconductor memory device, comprising:

a random access memory cell array including memory cells;

data access means operatively connected to said memory cell array and including;

one or more register circuit arrays, each having a data input and output circuit for simultaneously storing or reading data into or from said memory cells; and

a data output circuit for serially reading a plurality of data from said memory cells; and

one or more data modification circuits, each operatively connected to said corresponding register circuit array of said data access means, including at least one logical gate circuit and, successively receiving data from said data output circuit, modifying said receive data in a predetermined manner defined by said logical gate circuit and transmitting said modified data to said data input and output circuit.

2. A semiconductor memory device according to claim 1, wherein said data input and output circuit includes:

first gates connected in parallel with each other and a first terminal of each first gate operatively connected to a corresponding memory cell selection line and each having a second terminal;

first registers connected in parallel with each other and each connected to the second terminal of the corresponding gate; and

a gate drive circuit driving simultaneously said first gates to simultaneously store or read said plurality of data into or from said memory cells.

3. A semiconductor memory device, comprising:

a random access memory cell array including memory cells;

data access means operatively connected to said memory cell array and including;

one or more register circuit arrays, each having a data input and output circuit for simultaneously storing or reading data into or from said memory cells, each data input and output circuit including;

first gates connected in parallel with each other and a first terminal of each first gate operatively connected to a corresponding memory cell selection line and each having a second terminal;

first registers connected in parallel with each other and each connected to the second terminal of the corresponding gate; and

a gate drive circuit driving simultaneously said first gates, to simultaneously store or read data into or from said memory cells; and

a data output circuit for serially reading plurality of data from said memory cells, said data output circuit including;

second gates connected in parallel with each other and each having first and second terminals;

second registers connected to said second gates;

an output amplifier connected to said second registers; and

a gate drive circuit connected to said second gates; and

the first terminal of each of said second gates operatively connected to a corresponding memory cell selection line and the second terminal connected to a corresponding register of said second registers, in data transfer mode, each of said registers operable independently of each other, said gate drive circuit simultaneously driving said second gates to simultaneously store data of said memory cells into said second registers, and in a data output mode, said second registers successively output stored data therein to said output amplifier; and

one or more data modification circuits, each operatively connected to said corresponding register circuit array of said data access means, and successively receiving the data from said data output circuit, modifying said received data in a predetermined manner and transmitting said modified data to said data input and output circuit.

4. A semiconductor memory device according to claim 3, wherein said data modification circuit includes a logical operation circuit for a logical operation on one bit data from said data output circuit.

7. A semiconductor memory device according to claim 3, wherein said first registers comprise shift registers.

8. A semiconductor memory device according to claim 3, wherein said plurality of first registers comprise flip-flops.

5. A semiconductor memory device, comprising:

a random access memory cell array including memory cells;

data access means operatively connected to said memory cell array and including;

one or more register circuit arrays, each having a data input and output circuit for simultaneously storing or reading data into or from said memory cells, each data input and output circuit including;

first gates connected in parallel with each other and a first terminal of each first gate operatively connected to a corresponding memory cell selection line and each having a second terminal;

first registers connected in parallel with each other and each connected to the second terminal of the corresponding gate, said first registers comprising shift registers; and

a gate drive circuit driving simultaneously said first gates, to simultaneously store or read said data into or from said memory cells; and

a data output circuit for serially reading data from said memory cells; and

one or more data modification circuits, each operatively connected to said corresponding register circuit array of said data access means, and successively receiving the data from said data output circuit, modifying said receiving data in a predetermined manner and transmitting said modified data to said data input and output circuit.

6. A semiconductor memory device, comprising:

a random access memory cell array including memory cells;

data access means operatively connected to said memory cell array and including;

one or more register circuit arrays, each having a data input and output circuit for simultaneously storing or reading data into or from said memory cells, each data input and output circuit including;

first gates connected in parallel with each other and a first terminal of each first gate, operatively connected to a corresponding memory cell selection line and each having a second terminal;

first registers connected in parallel with each other and each connected to the second terminal of the corresponding gate, said first registers comprising flip-flops; and

a gate drive circuit driving simultaneously said first gates, to simultaneously store or read said data into or from said memory cells;

a data output circuit for serially reading data from said memory cells; and

one or more data modification circuits, each operatively connected to said corresponding register circuit array of said data access means, and successively receiving the data from said data output circuit, modifying said received data in a predetermined manner and transmitting said modified data to sid data input and output circuit.

9. A semiconductor memory device, comprising:

a random access memory cell array including memory cells;

data access means operatively connected to said memory cell array and including;

one or more register circuit arrays, each having a data input and output circuit for simultaneously storing or reading data into or from said memory cells;

a data output circuit for serially reading data from said memory cells, each data input and output circuit including;

first gates connected in parallel with each other and a first terminal of each first gate operatively connected to a corresponding memory cell selection line and each having a second terminal;

first registers connected in parallel with each other and each connected in the second terminal of the corresponding gate; and

a gate drive circuit driving simultaneously said first gates, to simultaneously store or read data into or from said memory cells; and

a designating circuit, connected to said second registers, for designating a predetermined range for data output from said data output circuit and restore in said input circuit, to perform a predetermined range of data modification; and

one or more data modification circuits, each operatively connected to said corresponding register circuit array of said data access means, and successively receiving the data from said data output circuit, modifying said received data in a predetermined manner and transmitting said modified data to said data input and output circuit.

10. A semiconductor memory device according to claim 9, wherein said designating circuit includes:

third gates connected to said second registers and in parallel with each other and each having first and second terminals;

third registers connected to said third gates; and

a decoder connected to said third registers,

the first terminal of each of said third gates connected to the corresponding register of said data output circuit for applying data in said output circuit to said data modification circuit and the second terminal connected to the corresponding register of said data input and output circuit for restoring data modified by said data modification circuit, and said third registers successively activating said third gates in response to a command decoded by said decoder.

11. A semiconductor memory device according to claim 10, wherein said third registers comprise shift registers.