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Method for improving wirability of master-image DCVS chips

  • US 4,742,471 A
  • Filed: 10/31/1985
  • Issued: 05/03/1988
  • Est. Priority Date: 10/31/1985
  • Status: Expired due to Fees
First Claim
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1. A method for improving the wirability of CMOS differential cascode voltage switch logic circuits, comprising a load and a plurality of differential switching pairs, which perform a predetermined Boolean logic function said method being operable to significantly reduce the number of wire crossings in the final logic circuit tree design and to allow as many of the internal tree connections as possible to be made using diffusion wiring, said method comprising;

  • first arranging the tree circuit to be optimized in an input format with the load at the top of the individual differential pairs, arranging said differential pairs in row and column format, initially defining an interconnection wiring pattern dictated solely by the requirements of the Boolean function being performed by the circuit, with the load and all differential pairs arranged with true and complement input, and outputs on the same side,next locating all of the differential pairs in rows corresponding to their logic level in the Boolean descriptions of the circuit,next relocating certain differential pairs to shorten interconnections, andnext mirroring certain differential pairs to eliminate line crossings, and finally, mirroring the entire logic circuit so produced whereby input and output connections may be altered to enhance interfacing with adjacent circuitry.

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