Method for improving wirability of master-image DCVS chips
First Claim
1. A method for improving the wirability of CMOS differential cascode voltage switch logic circuits, comprising a load and a plurality of differential switching pairs, which perform a predetermined Boolean logic function said method being operable to significantly reduce the number of wire crossings in the final logic circuit tree design and to allow as many of the internal tree connections as possible to be made using diffusion wiring, said method comprising;
- first arranging the tree circuit to be optimized in an input format with the load at the top of the individual differential pairs, arranging said differential pairs in row and column format, initially defining an interconnection wiring pattern dictated solely by the requirements of the Boolean function being performed by the circuit, with the load and all differential pairs arranged with true and complement input, and outputs on the same side,next locating all of the differential pairs in rows corresponding to their logic level in the Boolean descriptions of the circuit,next relocating certain differential pairs to shorten interconnections, andnext mirroring certain differential pairs to eliminate line crossings, and finally, mirroring the entire logic circuit so produced whereby input and output connections may be altered to enhance interfacing with adjacent circuitry.
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Abstract
A method for increasing the wirability of complementary metal oxide semiconductor (CMOS) differential cascode voltage switch (DCVS) logic circuits which comprises designing the circuitry to permit as many of the internal tree connections as possible to be wired using diffusion techniques. The method utilizes differential pair and load microblocks which have been designed so as to allow mirroring on a vertical center line. Utilizing the availability of mirroring for individual pairs plus relocation of individual pairs in the logic tree the crossings may be largely eliminated in a shortened period. It utilizes a step by step row and column analysis of the initial or starting tree design resulting from the basic Boolean logic to be performed by the particular circuit and makes required load mirroring and differential pair relocation decisions in an iterative process. The transistor pairs and load devices may be mirrored about a vertical center line. That is, they have an alternate configuration or layout in which left and right are reversed. The effect of mirroring is to reverse the points of connection for the true and complement inputs to the load, and to reverse the true and complement output locations of the pairs, WITHOUT switching the horizontal wiring tracks occupied by the inputs to the pairs, or outputs from the loads.
31 Citations
11 Claims
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1. A method for improving the wirability of CMOS differential cascode voltage switch logic circuits, comprising a load and a plurality of differential switching pairs, which perform a predetermined Boolean logic function said method being operable to significantly reduce the number of wire crossings in the final logic circuit tree design and to allow as many of the internal tree connections as possible to be made using diffusion wiring, said method comprising;
- first arranging the tree circuit to be optimized in an input format with the load at the top of the individual differential pairs, arranging said differential pairs in row and column format, initially defining an interconnection wiring pattern dictated solely by the requirements of the Boolean function being performed by the circuit, with the load and all differential pairs arranged with true and complement input, and outputs on the same side,
next locating all of the differential pairs in rows corresponding to their logic level in the Boolean descriptions of the circuit, next relocating certain differential pairs to shorten interconnections, and next mirroring certain differential pairs to eliminate line crossings, and finally, mirroring the entire logic circuit so produced whereby input and output connections may be altered to enhance interfacing with adjacent circuitry.
- first arranging the tree circuit to be optimized in an input format with the load at the top of the individual differential pairs, arranging said differential pairs in row and column format, initially defining an interconnection wiring pattern dictated solely by the requirements of the Boolean function being performed by the circuit, with the load and all differential pairs arranged with true and complement input, and outputs on the same side,
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2. A method for improving the wirability of CMOS differential cascode voltage switch logic circuits to significantly reduce the number of wire crossing in the final logic circuit tree design to allow as many of the internal tree connections as possible to be made using diffusion wiring, said method comprising;
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initially specifying a non-mirrored layout for the tree as required by the Boolean logic function performed by the tree, extracting for the tree the logical level of each of the pairs in the tree and their connectivity, assigning a row R to each switching pair equal to its logical level, assigning a column position C on each row to each pair by arbitrarily ordering from left to right all of the pairs on that row, the unmirrored convention being that the unmirrored load and all pairs have their true inputs and outputs at a first side, and their complement inputs and outputs at the other side, the mirrored or unmirrored conditions of the load and all pairs being specified by a value assigned to the constant ML and MP for the load and the individual pairs, respectively, the method branching to one of two possible procedures depending on the width C of the tree, when C=1 the procedure ONEWIDE being followed, otherwise MANYWIDE being followed, wherein the procedure ONEWIDE comprises; first examining each pair and if one or both drains connect to the load, then causing it to be SET so that the MP of the pair is specified such that the pair aligns with the load, examining each pair that has not been SET and if one or both drains connect to the same signal as the drains of a pair already SET, causing the current pair to be SET so that the MP of the current pair is specified so as to place the drain signal(s) on the same side as the drain signal(s) in that previously SET pair, and finally determining if the tree layout of this tree requires more than one vertical diffusion wiring track on a predetermined side of the tree, and if so, causing the entire tree, with its current values of ML and MP, to be mirrored so that the current values of ML and MP are replaced by their complements. - View Dependent Claims (3, 4, 5, 6, 7)
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8. A method for improving the wirability of CMOS differential cascode voltage switch logic circuits to significantly reduce the number of wire crossing in the final logic circuit tree design to allow as many of the internal tree connections as possible to be made using diffusion wiring, said method comprising;
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initially specifying a non-mirrored layout for the tree as required by the Boolean logic function performed by the tree, extracting for the tree the logical level of each of the pairs in the tree and their connectivity, assigning a row R to each switching pair equal to its logical level, assigning a column position C on each row to each pair by arbitrarily ordering from left to right all of the pairs on that row, the unmirrored convention being that the unmirrored load and all pairs have their true inputs and outputs at a first side, and their complement inputs and outputs at the other side, the mirrored or unmirrored conditions of the load and all pairs being specified by a value assigned to the constant ML and MP for the load and the individual pairs, respectively, determining if the width C of the tree is greater than 2 (C>
2) and if so;(1) first selecting as the initial subject for treatment a tree two columns wide wherein the leftmost two pairs in each row are processed, (2) determining for the topmost pair in each column, if the pair drains are connected only to the load, and if so, raising the pair to the highest row occurring for any pair in the tree unless the pair has gate variables in common with another pair in its original row, (3) for each row, starting from the second highest row in the tree and proceeding downward, calculating a preferred value of C for each pair in the row by averaging the Cs of the pairs (or load) to which it connects, considering both L1 and L0 as being at the center of the tree, (4) assigning pairs to columns as close as possible to the preferred columns, and always in the preferred order across the row, (5) repeating Step 2 with the new column assignments, (6) performing an initial mirroring operation comprising determining for each pair, if the right drain of the pair connects to a pair in a column which is to the left of the column of the pair to which the left drain connects and if so mirroring, the current pair (for this step, the load is assumed to be in the same column as the current pair), (7) performing the load mirroring, (8) performing the final pair mirroring for column 1, (9) performing the final pair mirroring for column 2, (10) mirror columns 3. . . n by repeating Step 9 wherein column 1 becomes column m and column 2 becomes column m+1, wherein m=2,3 . . . n-1 and m+1=3,4 . . . n until all n columns are processed.
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9. A method for improving the wirability of CMOS differential cascode voltage switch logic circuits to significantly reduce the number of wire crossings in the final logic circuit tree design to allow as many of the internal tree connections as possible to be made using diffusion wiring, said method comprising;
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(1) initially specifying a non-mirrored layout for the tree as required by the Boolean logic function performed by the tree, extracting for the tree the logical level of each of the pairs in the tree and their connectivity, (2) assigning a row R to each switching pair equal to its logical level, assigning a column position C on each row to each pair by arbitrarily ordering from left to right all of the pairs on that row, the unmirrored convention being that the unmirrored load and all pairs have their true inputs and outputs at a first side, and their complement inputs and outputs at the other side, the mirrored or unmirrored conditions of the load and all pairs being specified by a value assigned to the constant ML and MP for the load and the individual pairs, respectively, the method branching to one of two possible procedures depending on the width C of the tree, when C=1 the procedure ONEWIDE being followed, otherwise MANYWIDE being followed, wherein the procedure ONEWIDE comprises; (3) first examining each pair and if one or both drains connect to the load, then causing it to be SET so that the MP of the pair is specified such that the pair aligns with the load, (4) examining each pair that has not been SET and if one or both drains connect to the same signal as the drains of a pair already SET, causing the current pair to be SET so that the MP of the current pair is specified so as to place the drain signal(s) on the same side as the drain signal(s) in the previously SET pair, and (5) finally, determining if the tree layout of this tree requires more than one vertical diffusion wiring track on a predetermined side of the tree, and if so, causing the entire tree, with its current values of ML and MP, to be mirrored so that the current values of ML and MP are replaced by their complements, and
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10. Wherein the procedure MANYWIDE comprises;
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(6) first selecting as the initial subject for treatment a tree two columns wide wherein the leftmost two pairs in each row are processed, (7) determining for the topmost pair in each column, if the pair drains are connected only to the load, and if so, raising the pair to the highest row occurring for any pair in the tree unless the pair has gate variables in common with another pair in its original row, (8) for each row, starting from the second highest row in the tree and proceeding downward, calculating a preferred value of C for each pair in the row by averaging the Cs of the pairs (or load) to which it connects, considering both L1 and L0 as being at the center of the tree, (9) assigning pairs to columns as close as possible to the preferred columns, and always in the preferred order across the row, (10) repeating Step 7 with the new column assignments, and then proceeding to Step 11, (11) determining for each pair, if the right drain of the pair connects to a pair in a column which is to the left of the column of the pair to which the left drain connects and if so mirroring the current pair (for this step, the load is assumed to be in the same column as the current pair), Proceeding to a final load mirroring procedure which comprises; (12) determining if there are more connections from column-2 pairs to L1 than to L0, and if so, mirroring the load and proceeding to Step 16 else, continue, (13) repeating Step 12, but discounting any connections from a pair to the load if the pair to its left makes the same load connection, (14) determining if there is a column-2 pair which connects to L1 and which is on a higher row than all column-2 pairs which connects to L0, and if so, mirroring the load and proceeding to Step 17 else, continue, (15) finding the highest row on which there is no pair in column 2, but a higher row does contain a pair in column 2; and
in which the pair in column 1 connects to the load and determining if the column-1 pair makes a connection to L0 but not L1, and if so, mirroring the load,Proceeding to a final pair mirroring procedure which comprises; (16) utilizing as input the pair mirroring results of Step 15, (17) causing each column-1 pair connected to the load to be SET so that the pair aligns with the load, (18) examining each pair in column 1 which has not been SET, determining if one or both drains of a pair connect to the same signal(s) as the drain(s) of a pair already SET, and if so, causing the MP of the current pair to be SET to the same value as the MP of the previously SET pair, (19) examining each pair in column 1 which has not been SET, determining if a drain connects to the same signal as a drain of the pair in column 2 of the same row, and if so, causing the current column-1 pair to be SET to the MP value which will cause the drain with the shared signal to be on the right, (20) examining each pair in column 1 that has not been SET, determining if one or both drains connect to the same signal(s) as the drain(s) of a pair already SET, and if so, causing the MP of the current pair to be SET to the value that will place the drain signal(s) on the same side as the drain signal(s) in the previously SET pair, and (21) finally, causing all column-1 pairs which are not currently SET to be SET to their current MP values, (22) examining each pair in column 2 and determining if both drains connect to the same signals as the drains of the pair in column 1 of the same row, and if so, causing the MP of the current pair to be SET to the complement of the MP value of said pair in column 1, and when all pairs have been SET proceeding to Step 26 otherwise, (23) examining each pair in column 2 which connects to the load and has not been SET, determining if the right-hand drain of the pair in column 1 on the same row connects to the same load input as either of the drains in the current pair, and if so, causing the current pair to be SET to an MP value, which will cause the drain with the shared signal to be on the left, and when all pairs have been SET, proceeding to Step 26 otherwise, (24) examining each pair in column 2 which has not been SET, determining if the right-hand drain of a pair in column 1 of the same row connects to the same signal as either of the drains in the current pair, and if so, causing the current pair to be SET to an MP value which causes the drain with the shared signal to be on the left, and when all pairs have been SET, proceeding to Step 26 otherwise, (25) examining each pair in column 2 which has not been SET, determining if one or both drains connect to the same signal(s) as the drain(s) of a column-2 pair which has been SET, and if so, causing the current pair to be SET to an MP value which places the drain signal(s) of the current pair on the same side as the drain signal(s) in the previously SET pair, (26) examining the highest pair in column 2, determining if it has one and only one connection to the load and does not have the same drain connections as the pair on its left in the same row, if not, terminating the procedure as `complete`, and if so, causing the MP of the current pair to be SET to a value whereby the drain connected to the load is on the right, which `completes` the procedure, (27) finally, determining if the tree layout of this tree requires more than one vertical diffusion wiring track on a predetermined side of the tree, with its current values of ML and MP, to be mirrored so that the current values of ML and MP are replaced by their complements.
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11. A method for improving the wirability of CMOS differential cascode voltage switch logic circuits to significantly reduce the number of wire crossings in the final logic circuit tree design to allow as many of the internal tree connections as possible to be made using diffusion wiring, said method comprising;
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(1) initially specifying a non-mirrored layout for the tree as required by the Boolean logic function performed by the tree, extracting for the tree the logical level of each of the pairs in the tree and their connectivity, (2) assigning a row R to each switching pair equal to its logical level, assigning a column position C on each row to each pair by arbitrarily ordering from left to right all of the pairs on that row, the unmirrored convention being that the unmirrored load and all pairs have their true inputs and outputs at a first side, and their complement inputs and outputs at the other side, the mirrored or unmirrored conditions of the load and all pairs being specified by a value assigned to the constant ML and MP for the load and the individual pairs, respectively, the method branching to one of two possible procedures depending on the width C of the tree, when C=1 the procedure ONEWIDE being followed, otherwise MANYWIDE being followed, wherein the procedure ONEWIDE comprises; (3) first examining each pair and if one or both drains connect to the load, then causing it to be SET so that the MP of the pair is specified such that the pair aligns with the load, (4) examining each pair that has not been SET and if one or both drains connect to the same signal as the drains of a pair already SET, causing the current pair to be SET so that the MP of the current pair is specified so as to place the drain signal(s) on the same side as the drain signal(s) in the previously SET pair, and (5) finally, determining if the tree layout of this tree requires more than one vertical diffusion wiring track on a predetermined side of the tree, and if so, causing the entire tree, with its current values of ML and MP, to be mirrored so that the current values of ML and MP are replaced by their complements, which completes the procedure; Wherein the procedure MANYWIDE comprises; (6) first selecting as the initial subject for treatment a tree two columns wide wherein the leftmost two pairs in each row are processed, (7) determining for the topmost pair in each column, if the pair drains are connected only to the load, and if so, raising the pair to the highest row occurring for any pair in the tree unless the pair has gate variables in common with another pair in its original row, (8) for each row, starting from the second highest row in the tree and proceeding downward, calculating a preferred value of C for each pair in the row by averaging the Cs of the pairs (or load) to which it connects, considering both L1 and L0 as being at the center of the tree, (9) assigning pairs to columns as close as possible to the preferred columns, and always in the preferred order across the row, (10) repeating Step 7 with the new column assignments, and then proceeding to Step 11, (11) determining for each pair, if the right drain of the pair connects to a pair in a column which is to the left of the column of the pair to which the left drain connects and if so mirroring the current pair (for this step, the load is assumed to be in the same column as the current pair), Proceeding to a final load mirroring procedure which comprises; (12) determining if there are more connections from column-2 pairs to L1 than to L0, and if so, mirroring the load and proceeding to Step 6 else, continue, (13) repeating Step 12, but discounting any connections from a pair to the load if the pair to its left makes the same load connection, (14) determining if there is a column-2 pair which connects to L1 and which is on a higher row than all column-2 pairs which connects to L0, and if so, mirroring the load and proceeding to Step 17 else, continue, (15) finding the highest row on which there is no pair in column 2, but a higher row does contain a pair in column 2; and
in which the pair in column 1 connects to the load and determining if the column-1 pair makes a connection to L0 but not L1, and if so, mirroring the load,Proceeding to a final pair mirroring procedure which comprises; (16) utilizing as input the pair mirroring results of Step 15, (17) causing each column-1 pair connected to the load to be SET so that the pair aligns with the load, (18) examining each pair in column 1 which has not been SET, determining if one or both drains of a pair connect to the same signal(s) as the drain(s) of a pair already SET, and if so, causing the MP of the current pair to be SET to the same value as the MP of the previously SET pair, (19) examining each pair in column 1 which has not been SET, determining if a drain connects to the same signal as a drain of the pair in column 2 of the same row, and if so, causing the current column-1 pair to be SET to the MP value which will cause the drain with the shared signal to be on the right, (20) examining each pair in column 1 that has not been SET, determining if one or both drains connect to the same signal(s) as the drain(s) of a pair already SET, and if so, causing the MP of the current pair to be SET to the value that will place the drain signal(s) on the same side as the drain signal(s) in the previously SET pair, and (21) finally, causing all column-1 pairs which are not currently SET to be SET to their current MP values, (22) examining each pair in column 2 and determining if both drains connect to the same signals as the drains of the pair in column 1 of the same row, and if so, causing the MP of the current pair to be SET to the complement of the MP value of said pair in column 1, and when all pairs have been SET proceeding to Step 26 otherwise, (23) examining each pair in column 2 which connects to the load and has not been SET, determining if the right-hand drain of the pair in column 1 on the same row connects to the same load input as either of the drains in the current pair, and if so, causing the current pair to be SET to an MP value, which will cause the drain with the shared signal to be on the left, and when all pairs have been SET, proceeding to Step 26 otherwise, (24) examining each pair in column 2 which has not been SET, determining if the right-hand drain of a pair in column 1 of the same row connects to the same signal as either of the drains in the current pair, and if so, causing the current pair to be SET to an MP value which causes the drain with the shared signal to be on the left, and when all pairs have been SET, proceeding to Step 26 otherwise, (25) examining each pair in column 2 which has not been SET, determining if one or both drains connect to the same signal(s) as the drain(s) of a column-2 pair which has been SET, and if so, causing the current pair to be SET to an MP value which places the drain signal(s) of the current pair on the same side as the drain signal(s) in the previously SET pair, (26) examining the highest pair in column 2, determining if it has one and only one connection to the load and does not have the same drain connections as the pair on its left in the same row, if not, terminating the procedure as `complete`, and if so, causing the MP of the current pair to be SET to a value whereby the drain connected to the load is on the right, which `completes` the procedure, (27) finally, determining if the tree layout of this tree requires more than one vertical diffusion wiring track on a predetermined side of the tree, with its current values of ML and MP, to be mirrored so that the current values of ML and MP are replaced by their complements.
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Specification