Multiple port memory array device including improved timing and associated method

• US 4,742,493 A
• Filed: 05/19/1986
• Issued: 05/03/1988
• Est. Priority Date: 05/19/1986
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Schumann, Steve, Liu, Woei-Jian, Kok, Moon-Seng, Lewallen, Kent D.
• Primary Examiner(s): Moffitt, James W.
• Application Number:
  US06/864,690
• Time in Patent Office: 715 Days
• Field of Search: 365/49, 365/189, 365/230
• US Class Current: 365/233.5
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

An integrated circuit device which includes a memory array comprising a plurality of respective memory locations for storing binary data, each respective memory location corresponding to a respective combination of binary address signals, the device further comprising: at least two respective ports for receiving respective combinations of binary address signals corresponding to respective locations of said memory array; transition detection and signal providing circuitry for detecting a change in a respective binary address signal combination received by either a first or second of the at least two ports and for providing a first transition signal in response to a change in a respective first combination of binary address signals received by the first port and for providing a second respective transition signal in response to a change in a respective second combination of binary address signals received by the second port; and contention detection and signal providing means for receiving the first and the second transition signals and for detecting a match in the first and second combinations of binary address signals and for providing a respective first status signal in an inactive state in response to the first transition signal and for providing a respective second status signal in an inactive state in response to the second transition signal.

Claims

1. An Integrated circuit device including a memory array comprising a plurality of respective memory locations for storing binary data, each respective memory location corresponding to a respective combination of binary address signals, said device further comprising:

at least two respective port means for receiving respective combinations of binary address signals corresponding to respective locations of said memory array;

transition detection and signal providing means for detecting a change in a respective combination of binary address signals received by either a first or a second of said at least two port means, and for providing a first transition signal in response to a change in a respective first combination of address signals received by said first port means and for providing a second transition signal in response to a change in a respective second combination of address signals received by said second port means; and

address match means for receiving said first and second combinations of binary address signals and for providing a match signal in response to a match in said first and second combinations; and

status signal providing means for receiving said first and second transition signals and said match signal and for providing a first status signal in an inactive state during a first period of time in response to a provision of said first transition signal whether or not a match signal is received substantially during said first period of time, and for providing a second status signal in an inactive state during a second period of time in response to a provision of said second transition signal whether or not a match signal is received substantially during said second period of time, and for substantially providing either only said first status signal or only said second status signal in an active state in response to a match signal substantially after said first and said second periods of time.

2. The device of claim 1 wherein said address match means comprises comparator means.

3. The device of claim 1, further comprising:

priority means for providing a priority signal to said status signal providing means which causes said status signal providing means to substantially provide either only said respective first or only said respective second status signal in an active state in response to said match signal substantially after said first and second periods of time.

4. The device of claim 1 wherein:

substantially during said first period of time said first combination of address signals can substantially settle to a new first combination of signals; and

substantially during said second period of time said second combination of address signals can substantially settle to a new second combination of signals.

5. The device of claim 4 wherein said transition detection and signal providing means can provide said first transition signal substantially throughout said first period of time and can provide said second transition signal substantially throughout said second period of time.

6. The device of claim 1 wherein said transition detection and signal providing means comprises:

means for providing a first signal pulse in response to at least one change in the respective first combination of address signals;

means for receiving said first signal pulse and for providing said first transition signal substantially throughout said first time period, wherein said first time period expires after said first signal pulse ends;

means for providing a second signal pulse in response to at least one change in the respective second combination of address signals; and

means for receiving said second signal pulse and for providing said second transition signal substantially throughout said second time period, wherein said second time period expires after said first signal pulse ends.

7. An integrated circuit device including a memory array comprising a plurality of respective memory locations for storing binary data, each respective memory location corresponding to a respective combination of binary address signals, said device further comprising:

at least two respective port means for receiving respective combinations of binary address signals corresponding to respective locations of said memory array;

transition detection and signal providing means including,

means for providing a first signal pulse in response to at least one change in the respective first combination of address signals,

means for receiving said first signal pulse and for providing a first transition signal substantially throughout a first time period, wherein said first time period expires after said first signal pulse ends,

means for providing a second signal pulse in response to at least one change in the respective second combination of address signals,

means for receiving said second signal pulse and for providing a second transition signal substantially throughout a second time period wherein said second time period expires after said second signal pulse ends;

address match means for receiving said first and second combinations of binary address signals and for providing a match signal in response to a match in said first and second combinations;

status signal providing means for receiving said first and second transition signals and said match signal and for providing a first status signal in an inactive state during said first period of time in response to a provision of said first transition signal whether or not a match signal is received substantially during said first period of time, and for providing a second status signal in an inactive state during said second period of time in response to a provision of said second transition signal whether or not a match signal is received substantially during said second period of time, and for substantially providing either only said first status signal or only said second status signal in an active state in response to a match signal substantially after said first and said second periods of time; and

priority means for receiving said first and second signal pulses and for providing a priority signal to said status signal providing means, said priority signal determining whether only said respective first or only said respective second status signal is provided in an active state in response to said match signal substantially after said first and said second periods of time.

8. A method for controlling access to respective ports of a multiple port integrated circuit memory array including a plurality of respective memory locations, each memory location corresponding to a respective combination of binary address signals, comprising the following steps:

receiving a first combination of binary address signals and a second combination of binary address signals;

detecting a change in said first combination;

detecting a change in said second combination;

providing a first transition signal in response to a change in said first combination;

providing a second transition signal in response to a change in said second combination;

determining whether there is a match in said first and second combinations of binary address signals and providing a match signal in response to a match;

substantially during a first period of time, providing a first status signal in an inactive state in response to said first transition signal;

substantially during a second period of time, providing a second status signal in an inactive state in response to said second transition signal; and

in response to said match signal and substantially after said respective first and second periods of time, providing either only said first status signal or only said second status signal in an active state.

9. The method of claim 8 wherein:

during said first period of time said first combination of address signals can substantially settle to a new first combination of signals; and

during said second period of time said second combination of address signals can substantially settle to a new second combination of signals.

10. The method of claim 9 wherein:

said step of providing a first transition signal provides said first transition signal substantially throughout said first time period; and

said step of providing a second transition signal provides said second transition signal substantially throughout said second time period.