High speed binary data communication system

• US 4,742,532 A
• Filed: 05/08/1986
• Issued: 05/03/1988
• Est. Priority Date: 05/08/1986
• Status: Expired due to Term

• Current Assignee: Walker, Harold R.
• Original Assignee: Walker, Harold R.
• Inventors: Walker, Harold R.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/861,049
• Time in Patent Office: 726 Days
• Field of Search: 375/50, 375/52, 375/56, 375/57, 375/61, 375/77, 375/81, 375/83, 375/60, 375/121, 375/43, 455/42, 455/47, 455/109, 455/202, 455/204, 360/30, 360/40, 360/43, 360/44, 332/9 R, 332/16 R, 332/23 R, 332/44, 329/104, 329/122, 329/123, 330/295, 330/303, 330/306, 333/167, 333/175, 333/178
• US Class Current: 375/277
• CPC Class Codes: H04L 27/2035 using a single or unspecified number of carriers
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence

Abstract

There is disclosed a high speed data transmission system for transmitting a binary data signal over a communications path. The binary data signal is clocked at a given period. The system comprises encoded means responsive to a binary NRZ input data signal to provide at an output an encoded digital signal having time periods greater than multiples of the clock period, whereby the encoded signal occupies a lesser effective bandwidth than the NRZ signal would occupy. There are balanced modulator means having an input responsive to the encoded signal and another input adapted to receive a carrier frequency to provide at an output a double sideband suppressed carrier signal. Coupled to the output of the balanced modulator are narrow bandwidth filtering means including first low pass and second high pass parallel filter paths each having a common input terminal coupled to the output of the modulator. The ouputs of the low and high pass filters are symmetrically combined to provide a narrow single sideband signal for transmission characterized in that transitions between binary levels in said encoded signal are manifested by distinct phase changes in said single sideband signal.

Claims

1. A high speed data transmission system for transmitting a binary data signal over a communications path, said binary data signal clocked at a given period, comprising:

encoding means responsive to a binary NRZ input data signal to provide at an output an encoded digital signal having time periods greater than multiples of said clock period and at a given bit rate whereby said encoded signal occupies a lesser effective bandwidth than said NRZ signal alone, said lesser effective bandwidth being 1/2 to 1/3 that of said NRZ signal;

balanced modulator means having an input responsive to said encoded signal and another input adapted to receive a carrier frequency signal to provide at an output a double sideband suppressed carrier signal shifting in phase 180 degrees with changes in said encoded signal;

filtering means coupled to said output of said balanced modulator to provide a narrow bandwidth less than 1/2 the maximum bandwidth of said sideband signal and by which said carrier frequency and low frequencies are prevented from propagating to reject all sideband frequency components which are lower than 1/4 the bit rate and which are higher than 1/2 the bit rate of said encoded signal to provide at an output a narrow sideband signal for transmission characterized in that transitions between binary levels in said encoded signal are manifested by distinct phase changes in said single sideband signal, said filtering means operative to minimize phase distortion within the sideband signal, while passing only a part of one of said sidebands.

2. The high speed data transmission system according to claim 1, wherein said encoded digital signal has time periods of 2, 3 and 4 times said clock period, resulting in sideband frequencies of 1/2, 1/3 and 1/4 of said clock frequency.

3. The high speed data transmission system according to claim 1, wherein said encoded digital signal has time periods of 2, 2.5 and 3 times said clock period, resulting in sideband frequencies of 1/2, 1/2.5 and 1/3 of said clock frequency.

4. The high speed data transmission system according to claim 1, wherein said filtering means comprises a first and a second parallel filter path each having a common input terminal coupled to said output terminal of said modulator, with said first filter path including a low pass filter and said second filter path including a high pass filter, with the output of said first path coupled to the output of said second path via coupling means operative to symmetrically combine the filtered outputs from said first and second paths to provide said single sideband signal, wherein said low pass filter exhibits a phase shift of relatively 90°

at frequencies different from said carrier frequencies with said high pass filter exhibiting a phase shift of relatively 90° and

of opposite sign to said low pass filter with both said low and high pass filters exhibiting the same numeric value phase shift at said carrier frequency, with said outputs of said filters being combined in phase to be additive in such a manner as to cancel phase changes at the output over the center pass band of the filter.

5. The high speed data transmission system according to claim 4, wherein said low pass filter comprises a first inductor having first and second terminals, with said first terminal coupled to said common input terminal and said second terminal coupled to a point of reference potential via a first capacitor to form a first resonant circuit and wherein said high pass filter comprises a second capacitor having first and second input terminals with said first input terminal coupled to said common terminal and said second terminal coupled to a point of reference potential via a second inductor to form a second resonant circuit, with said first circuit resonant at a frequency equal to or higher than the center frequency to be passed, and with said second circuit resonant at a frequency equal to or lower than the center frequency to be passed.

6. The high speed data transmission circuit according to claim 5, further according a first amplifier having an input terminal and an output terminal, with said input terminal coupled to said second terminal of said first inductor, a second amplifier having an input terminal and an output terminal, with said input terminal coupled to said second terminal of said second capacitor and means coupling said output terminals of said first and second amplifiers to one another, to cause output signals from said amplifiers to combine to pass said single sideband signal within a narrow bandwidth.

7. The high speed data transmission circuit according to claim 6, further including first means coupled to said first amplifier for controlling the gain thereof and second means coupled to said second amplifier for controlling the gain thereof, to enable the outputs to be balanced thereby obtaining maximum phase correction.

8. The highspeed data transmission circuit according to claim 6, wherein said means coupling said output terminals of said first and second amplifiers comprises a first resistor having one terminal coupled to said output terminal of said first amplifier and a second resistor having one terminal coupled to said output terminal of said second amplifier, with the other terminal of said first and second resistors coupled to one another to provide a combined output terminal for said single sideband signal.

9. The high speed data transmission circuit according to claim 5, wherein said first and second amplifiers are operational amplifiers having high input impedances at said input terminals to minimize loading to said first and second resonant circuits, and having low output impedances to permit combining of said output signals.

10. The receiving means for a high speed data transmission system according to claim 1, further comprising:

limiting means having an input terminal responsive to said single sideband output signal for providing a limited output having a uniform level of said single sideband signal;

phase change detecting means responsive to said limited replica signal to provide at an output a series of pulses indicative of changes in said phase angles in said single sideband signal; and

decoding means coupled to said output of said phase change detecting means to provide a replica of said binary NRZ signal.

11. The high speed data transmission system according to claim 10, further including control means coupled to said limiting means to vary the level at which limiting occurs.

12. The high speed data transmission system according to claim 10, wherein said phase detecting means includes an OR gate having a first input coupled to said output of said limiting means, and a second input;

a voltage controlled oscillator operative to provide at an output a signal indicative of the frequency within a narrowed single sideband signal and having said output coupled to said second input of said OR gate, to cause said gate to provide at an output a signal indicative of the phase changes in said narrowed single sideband signal, and means coupled to the output of said OR gate to control the frequency of said oscillator.

13. The high speed data transmission system according to claim 12, further including decoding means having an input coupled to said output of said OR gate to provide at an output a replica of said binary NRZ data signal.

14. The high speed data transmission system according to claim 12, further including a low pass filter coupled to said output of said OR gate.

15. The high speed data transmission system according to claim 12, wherein said OR gate is an exclusive OR gate.

16. In a high speed data transmission system for transmitting a binary NRZ data signal over a communications path, said signal transmitted as a narrow single sideband signal characterized in that there are distinct phase angle changes in said signal indicative of binary data transitions as from a zero to a one or a one to a zero, said sideband signal as transmitted being completely devoid of a carrier frequency and having only a portion of a sideband containing NRZ information in combination therewith, decoding means for such a single sideband signal, comprising:

a limiter having an input adapted to receive said single sideband signal for providing at an output a limited version of said signal;

a phase change detector means having an input coupled to said output of said limiter and having a voltage controlled oscillator tuned to the approximate center frequency of said sideband signal for providing a signal consisting of pulses at the output indicative of said distinct phase angle changes, and

decoding means coupled to the output of said phase change detector means for restoring a binary NRZ data signal from said pulses.

17. A method of encoding a binary NRZ data signal at a given clock rate to a binary data output signal of a lesser bandwidth comprising the steps of:

(a) detecting when a bit of said NRZ signal is at a given binary state;

(b) determining whether said bit at said state is to be repeated;

(c) providing a crossover in said data output signal 4/4 bit periods later after first detecting said bit if said bit is to be repeated;

(d) detecting a change of said state in said NRZ signal;

(e) providing a crossover in said data output signal 5/4 bit periods later after detecting said change in state indicative of said change,

(f) counting the change of state in said NRZ to determine 4 changes in state;

(g) providing an indication of 4 changes indicative of a missing bit in said output signal,

(h) determining the binary state of said missing bit to provide a 6/4 bit period delay in said output signal for one binary state and no delay for said other binary state, and restoring said missing bit.

18. The method according to claim 17, wherein said one binary state is a binary zero with said other state being a binary one.

19. The method according to claim 17, comprising the step of detecting said 6/4 bit period delay in said binary data output signal to determine a reset condition to enable said counting step to again determine 4 changes in state.