Pulse width modulator circuit for switching regulators

• US 4,743,783 A
• Filed: 08/25/1986
• Issued: 05/10/1988
• Est. Priority Date: 01/16/1984
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Davis, Walter R., Isbell, Tim D.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Callahan, Timothy P.
• Application Number:
  US07/001,321
• Time in Patent Office: 624 Days
• Field of Search: 307/498, 307/494, 307/529, 307/261, 307/355, 307/356, 307/357, 307/362, 307/364, 328/159, 328/158, 330/69, 330/252, 330/300, 330/260
• US Class Current: 327/361
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A circuit for pulse width modulating the output of a voltage controlled oscillator without introducing any ocillator frequency or amplitude (slope) modulation. A summing circuit is combined with a comparator and provided with inputs that accommodate differential sum/difference inputs, an error input and a ramp input from the oscillator or other source. The ramp and error signals are combined differentially to pulse width modulate the comparator output and pulse width modulation can also be achieved by via the sum/difference inputs a differential relationship.

Claims

1. A circuit for signal summing useful in pulse width modulators, said circuit comprising:

first and second power supply terminals connectable to a source of operating power;

a first transistor having a base coupled to a first signal voltage source, an emitter coupled to one terminal of a first scaling and linearizing resistor, and a collector coupled to one terminal of a first load element;

a second transistor having a base coupled to a second voltage signal source, an emitter coupled to one terminal of a second scaling and linearizing resistor, and a collector coupled to one terminal of a second load element;

means for coupling the other terminals of said first and second load elements to said first power supply terminal;

means for coupling the other terminals of said first and second scaling and linearizing resistors respectively through first and second constant current devices to said second power supply terminal;

a third transistor having a collector coupled to said collector of said first transistor, an emitter coupled to one terminal of a third scaling and linearizing resistor, and a base coupled to a third voltage signal source;

a fourth transistor having a collector coupled to said collector of said second transistor, an emitter coupled to one terminal of a fourth scaling and linearizing resistor, and a base coupled to a fourth voltage signal source;

means for coupling the other terminals of said third and fourth scaling and linearizing resistors respectively through third and fourth constant current devices to said second power supply terminal whereby said first and third voltage signal sources are summed in said first load element and said second and fourth voltage signal sources are summed in said second load element.

2. The circuit of claim 1 further comprising:

a first coupling resistor coupled between said other ends of said first and second linearizing resistors; and

a second coupling resistor coupled between said other ends of said third and fourth linearizing resistors whereby said first and second voltage signal sources are combined differentially and said third and fourth voltage signal sources are combined differentially.