Random access memory cell with MIS capacitor having insulator of oxide of doped metal

• US 4,743,953 A
• Filed: 08/06/1986
• Issued: 05/10/1988
• Est. Priority Date: 12/29/1980
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Toyokura, Nobuo, Taguchi, Masao
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US06/894,509
• Time in Patent Office: 643 Days
• Field of Search: 357/23.6, 357/23.11, 357/41, 357/54
• US Class Current: 257/310
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/2254 from or through or into an applied layer, e.g. photoresist, nitrides
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/31683 of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A semiconductor device such as a MIS type capacitor which including a semiconductor substrate of one conductive sign (p-type silicon substrate), a region (n-type) of conductive sign opposite to that of the substrate formed in the substrate, an electrode making up a capacitor formed on the substrate apart from the region of opposite conductive sign and a transfer gate formed between the capacitor and the region of opposite conductive sign. The device is fabricated according to the invention such that the insulating film is formed under the electrode and has substantially the same planar form as the electrode, the insulating film contains impurities of a conductive sign opposite to that of the substrate and the region of opposite conductive sign is formed where the insulating film is in contact with the substrate. The region of opposite conductive sign is formed accurately in a self-alignment fashion. Such insulating film is made of an oxide or a nitride of at least one metal selected from the group consisting of Ta, Ti, Hf, Nb, Zr and Al.

Claims

1. A semiconductor device, comprising:

a substrate of one conductivity type;

a first region formed in said substrate of a conductivity type opposite to that of said substrate;

an electrode comprising a capacitor formed over said substrate at a position apart from said first region; and

a transfer gate formed between said capacitor and said first region of opposite conductivity type;

wherein said capacitor comprises;

an insulating film formed under said electrode in substantially the same planar shape as said electrode, said insulating film comprising an oxide of a doped metal selected from a group of metals comprising tantalum, titanium, zirconium and hafnium, containing dopant impurities of a conductivity type opposite to that of said substrate, and having a reduced grain size of the metal oxide as compared to the metal oxide doped after oxidation; and

a second region of said opposite conductivity type formed in said substrate where said insulating film is in contact with said substrate.

2. A semiconductor device of claim 1, wherein said second region and said electrode are self-aligned by heat treating said insulating film first at a temperature within the range of 500°

to 700°

C. when forming the oxide, and then at approximately 1000°

C. to form said second region of opposite conductivity type.

3. A semiconductor device of claim 1, wherein said insulating film is patterned and said second region of opposite conductivity type is formed self-aligned when the heat treatment is carried out after patterning of said insulating film.

4. A semiconductor device, comprising:

a substrate of a first conductivity;

a first layer formed on said substrate and comprising an oxide of a doped metal and having a reduced grain size of the metal oxide as compared to the metal oxide doped after oxidation;

a second layer formed over said first layer and comprising a material capable of withstanding a diffusion process of at least 900°

C.; and

a region of a second conductivity opposite to the first conductivity formed in said substrate by diffusion of the impurity in said first layer into said substrate.

5. A semiconductor device of claim 4, wherein the impurity is selected from the group consisting of phosphorous and arsenic.

6. A semiconductor device of claim 5, wherein the material capable of withstanding a diffusion process of at least 900°

C. is selected from the group consisting of molybdenum silicide and polycrystalline silicon.

7. A semiconductor device of claim 6, wherein said first layer comprises a plurality of said first layers.

8. A semiconductor device of claim 6, further comprising a silicon nitride layer formed between said first and second layers.

9. A semiconductor device of claim 7 or 8, further comprising:

a first insulating layer formed on said second layer;

a transfer gate formed on said insulating layer;

a data line formed in said substrate;

a second insulating layer formed on said transfer gate and said data line; and

a conductor formed on said second insulating layer and in contact with said transfer gate.