Transform processor system having post processing

• US 4,744,042 A
• Filed: 11/30/1984
• Issued: 05/10/1988
• Est. Priority Date: 12/28/1970
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/676,769
• Time in Patent Office: 1,257 Days
• Field of Search: 364/726
• US Class Current: 708/404
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 13/12 : using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

An incremental digital filter provides high speed and low cost capability such as for performing fast Fourier transforms (FFTs), correlations, convolutions, and other digital filter operations. One configuration operates at microwave sample rates, computing a complete 512-point FFT in 0.2 microseconds for an effective sample rate of 2.56 gigahertz. High speed and low cost are derived from a parallel pipeline architecture in combination with incremental processing. Parallel pipeline architecture provides extremely high speed while the incremental mechanization provides a simple arrangement with a low component count for low cost. The incremental nature of the processor provides an integrating type mechanization, where integration-after-transformation yields high processing gain for signal-to-noise-ratio enhancement.

High data rate input and output mechanizations are provided to accommodate the high processing rates. An improved input mechanization involves analog signal to incremental digital conversion. An improved output mechanization involves integration after filtering for data rate reductions and for signal enhancement and also involves a bus output structure for multiplexing of output parameters.

Claims

1. A transform processor system comprising:

a time domain circuit for generating time domain signal samples;

a transform processor for processing the time domain signal samples to generate transforms, each transform having a plurality of frequency domain signal samples; and

a post processor for integrating the frequency domain signal samples, said post processor including an adder for adding each of the plurality of the frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain a plurality of integrated frequency domain signal samples.

2. The system as set forth in claim 1 above, further comprising a radar receiver for generating a sequential radar signal;

wherein said time domain circuit includes a charge coupled device for generating parallel time domain input signal samples in response to the sequential radar signal and an incremental input circuit for generating the time domain signal samples as incremental parallel time domain signal samples in response to the parallel time domain input signal samples generated with said charge coupled device;

wherein said transform processor includes wired constant circuit for storing constant numbers and a parallel Fourier transform processor for generating the transforms of the time domain signal samples as incremental Fourier transforms in parallel processing form in response to the constant numbers stored in said wired constant circuit and in response to the incremental parallel time domain signal samples, each incremental Fourier transform having a plurality of incremental Fourier frequency domain signal samples generated in response to the incremental parallel time domain signal samples that are generated with said incremental input circuit;

wherein said system further comprises

a coherent incremental frequency domain integrator for incrementally coherently integrating the incremental Fourier frequency domain signal samples with an incremental reference signal;

a coherent adder for coherently adding each of the plurality of integrated incremental frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the integrated incremental frequency domain signal samples in a different one of the transforms generated with said Fourier transform processor to obtain a plurality of coherent multi-bit digital integrated frequency domain signal samples;

a data link for communicating the plurality of coherent multi-bit digital integrated frequency domain signal samples to a remote location; and

a stored program digital computer being located at the remote location for processing the plurality of coherent multi-bit digital integrated frequency domain signal samples that are communicated with said data link under control of a stored program.

3. The system as set forth in claim 1 above, wherein said time domain circuit includes a complex time domain circuit for generating complex pairs of real and imaginary time domain signal samples, wherein said transform processor includes a complex signal processor for transform processing the pairs of real and imaginary time domain signal samples to generate transforms, each transform having a plurality of pairs of real and imaginary frequency domain signal samples, and wherein said post processor includes a coherent integrator for coherently integrating the frequency domain signal samples.

4. A transform system comprising:

a charge coupled device time domain circuit for generating parallel time domain signal samples, said charge coupled device time domain circuit including a serial input circuit for generating serial time domain input signal samples and a parallel output circuit for generating the parallel time domain signal samples;

a transform processor for processing the parallel time domain signal samples to generate transforms, each transform having a plurality of frequency domain signal samples; and

a post processor for integrating the frequency domain signal samples, said post processor including an adder for adding each of the plurality of the frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain a plurality of integrated frequency domain signal samples.

5. A transform processor system comprising:

an incremental time domain circuit for generating incremental time domain signal samples;

an incremental transform processor for processing the incremental time domain signal samples to generate transforms each transform having a plurality of incremental frequency domain signal samples; and

an incremental post processor for integrating the incremental frequency domain signal samples, said incremental post processor including an incremental adder for incrementally adding each of the plurality of the incremental frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the incremental frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain a plurality of integrated frequency domain signal samples.

6. A fast Fourier transform system comprising:

an incremental parallel time domain input circuit for generating incremental parallel time domain signal samples;

an incremental parallel fast Fourier transform processor for processing the incremental parallel time domain signal samples to generate incremental parallel fast Fourier transforms, each incremental parallel fast Fourier transform having a plurality of incremental frequency domain signal samples; and

an incremental post processor for incrementally integrating the frequency domain signal samples, said incremental post processor including an incremental adder for incrementally adding each of the plurality of the incremental frequency domain signal samples in one of the incremental parallel fast Fourier transforms generated with said incremental parallel fast Fourier transform processor to a corresponding one of the plurality of the incremental frequency domain signal samples in a different one of the incremental parallel fast Fourier transforms generated with said incremental parallel fast Fourier transform processor to obtain a plurality of integrated frequency domain signal samples.

7. A transform processor system comprising:

a time domain circuit for generating time domain signal samples having a first resolution;

a transform processor for processing the time domain signal samples to generate transforms, each transform including a plurality of frequency domain signal samples having a second resolution that is better than the first resolution of the time domain signal samples; and

a post processor for integrating the frequency domain signal samples, said post processor including an adder for adding each of the plurality of the frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the frequency domain signal samples in a different one of the transforms generated with said transforms processor to obtain a plurality of integrated frequency domain signal samples.

8. A transform processor system comprising:

a parallel input time domain circuit for generating parallel time domain signal samples;

a parallel Fourier transform processor for processing the parallel time domain signal samples to generate parallel Fourier transforms, each parallel Fourier transform having a plurality of parallel frequency domain signal samples; and

a post processor for integrating the parallel frequency domain signal samples, said post processor including an adder for adding each of the plurality of the frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the frequency domain signal samples in a different one of the transforms generated with said trasnform processor to obtain a plurality of integrated frequency domain signal samples.

9. A transform processor system comprising:

a time domain circuit for generating time domain signal samples;

a transform processor for processing the time domain signal samples that are generated with said time domain circuit to generate transforms, each transform having a plurality of frequency domain signal samples; and

a frequency domain integrator for integrating the frequency domain signal samples, said frequency domain integrator including an adder for adding each of the plurality of the frequency domain signal samples in one of the transforms to a corresponding one of the plurality of the frequency domain signal samples in a different one of the transforms to obtain a plurality of integrated frequency domain signal samples.

10. A transform processor system comprising:

an incremental time domain input circuit for generating incremental time domain signal samples;

an incremental transform processor for processing the incremental time domain signal samples to generate transforms, each transform having a plurality of frequency domain signal samples; and

a post processor for integrating the frequency domain signal samples generated with said incremental transform processor, said post processor including an adder for adding each of the plurality of the frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain a plurality of multi-bit digital whole number integrated frequency domain signal samples.

11. The system as set forth in claim 10 above, further comprising a sonar receiver for generating a sequential sonar signal;

wherein said incremental time domain circuit includes a charge coupled device for generating parallel input time domain signal samples in response to the sequential sonar signal and an incremental input circuit for generating the incremental time domain signal samples as incremental parallel time domain signal samples in response to the parallel input time domain signal samples generated with said charge coupled device;

wherein said incremental transforms processor includes a wired constant circuit for storing constant numbers and a parallel incremental Fourier transform processor for generating the transforms of the time domain signal samples as incremental Fourier transforms in parallel processing form in response to the constant numbers stored in said wired constant circuit and in response to the incremental parallel time domain signal samples, each incremental Fourier transform having a plurality of incremental Fourier frequency domain signal samples generated in response to the incremental parallel time domain signal samples that are generated with said incremental input circuit;

wherein said system further comprises;

a coherent incremental frequency domain integrator for incrementally coherently integrating the incremental Fourier frequency domain signal samples;

a coherent adder for coherently adding each of the plurality of the integrated incremental frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the integrated incremental frequency domain signal samples in a different one of the transforms generated with said Fourier transform processor to obtain a plurality of coherent multi-bit digital integrated frequency domain signal samples;

a data link for communicating the plurality of coherent multi-bit digital integrated frequency domain signal samples that are generated with said post processor to a remote location; and

a stored program digital computer being located at the remote location for processing the plurality of coherent multi-bit digital integrated frequency domain signal samples that are communicated with said data link under control of a stored program.

12. The system as set forth in claim 10 above, wherein said time domain circuit includes a charge coupled device for generating the incremental time domain signal samples as parallel incremental time domain signal samples, said charge coupled device including a serial input circuit for generating serial time domain input signal samples and a parallel incremental output circuit for generating the parallel incremental time domain signal samples, wherein said incremental transform processor includes a parallel incremental transform processing circuit for processing the parallel incremental time domain signal samples to generate the transforms as parallel incremental transforms.

13. The system as set forth in claim 10 above, wherein said incremental time domain circuit includes a parallel incremental input circuit for generating the incremental time domain signal samples as incremental parallel time domain signal samples and wherein said incremental transform processor includes a parallel incremental Fourier transform processor for generating parallel incremental Fourier transforms of the parallel incremental time domain signal samples that are generated with said parallel incremental input circuit.

14. A fast Fourier transform processor system comprising:

an incremental time domain circuit for generating incremental time domain signal samples;

an incremental fast Fourier processor for processing the incremental time domain signal samples to generate incremental fast Fourier transforms, each incremental fast Fourier transform having a plurality of incremental frequency domain signal samples; and

an incremental post processor for integrating the incremental frequency domain siganl samples generated with said incremental fast Fourier transform processor, said incremental post processor including an incremental adder for incrementally adding each of the plurality of the incremental frequency domain signal samples in one of the incremental fast Fourier transforms generated with said incremental fast Fourier transform processor to a corresponding one of the plurality of the incremental frequency domain signal samples in a different one of the incremental fast Fourier transforms generated with said incremental fast Fourier trasnform processor to obtain a plurality of multi-bit digital whole number integrated frequency domain signal samples.

15. A fast Fourier transform system comprising:

an incremental time domain input circuit for generating incremental time domain signal samples;

an incremental fast Fourier transform processor for processing the incremental time domain signal samples to generate fast Fourier transforms, such fast Fourier transform having a plurality of multi-bit digital frequency domain signal samples having a resolution that is better than the resolution of the incremental time domain signal samples; and

a post processor for integrating the multi-bit digital frequency domain signal samples generated with said fast Fourier transform processor, said post processor including an adder for adding each of the plurality of multi-bit frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the frequency domain signal samples in a different one of the transforms generated with said incremental fast Fourier transform processor to obtain a plurality of integrated frequency domain signal samples.

16. A transform processor system comprising:

a complex incremental time domain circuit for generating complex pairs of incremental real and imaginary time domain signal samples;

a complex incremental transform processor for transform processing the pairs of incremental real and imaginary time domain signal samples to generate transforms, each transform having a plurality of pairs of incremental real and imaginary frequency domain signal samples; and

a coherent post processor for coherently integrating the frequency domain signal samples generated with said incremental transform processor, said post processor including an adder for adding each of the plurality of the frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain a plurality of multi-bit digital whole number integrated frequency domain signal samples.

17. A transform processor system comprising:

an incremental time domain input circuit for generating incremental time domain signal samples;

an incremental transform processor for processing the incremental time domain signal samples to generate transforms, each transform having a plurality of frequency domain signal samples; and

a frequency domain post processor for integrating the frequency domain signal samples generated with said incremental transform processor, said post processor including an adder for adding each of the plurality of the frequency domain signal samples in one of the transforms generated with said incremental transform processor to a corresponding one of the plurality of the frequency domain signal samples in a different one of the transforms generated with said incremental transforms processor to obtain a plurality of multi-bit digital whole number integrated frequency domain signal samples.

18. A transform processor system comprising:

a time domain circuit for generating time domain signal samples;

a transform processor for processing the time domain signal samples to generate frequency domain signal samples; and

a coherent post processor for coherently integrating the frequency domain signal samples generated with said transform processor.

19. The system as set forth in claim 18 above, further comprising a seismic receiver for generating a sequential seismic signal;

wherein said time domain circuit includes a charge coupled device for generating parallel time domain input signal samples in response to the sequential seismic signal and an incremental input circuit for generating the time domain signals samples as incremental parallel time domain signal samples in response to the parallel time domain input signal samples generated with said charge coupled device;

wherein said transform processor includes a wired constant circuit for storing constant numbers and a parallel Fourier transform processor for generating the transforms of the time domain signal samples as incremental Fourier transforms in parallel processing form in response to the constant numbers stored in said wired constant circuit and in response to the incremental parallel time domain signal samples, each incremental Fourier transform having a plurality of incremental Fourier frequency domain signal samples generated in response to the incremental parallel time domain signal samples that are generated with said incremental input circuit;

said system further comprising;

an incremental coherent frequency domain integrator for incrementally coherently integrating the incremental Fourier frequency domain signal samples, said incremental coherent frequency domain integrator including a coherent adder for coherently adding each of the plurality of the incremental frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the incremental frequency domain signal samples in a different one of the transforms generated with said Fourier transform processor to obtain a plurality of coherent multi-bit digital integrated frequency domain signal samples;

a data link for communicating the plurality of coherent multi-bit digital integrated frequency domain signal samples that are generated with said post processor to a remote location; and

a stored program digital computer being located at the remote location for processing the plurality of coherent multi-bit digital integrated frequency domain signal samples that are communicated with said data link under control of a stored program.

20. The system as set forth in claim 18 above, wherein said time domain circuit includes a charge coupled device for generating the time domain signal samples as parallel time domain signal samples, said charge coupled device including a serial input circuit for generating serial time domain input signal samples and a parallel output circuit for generating the parallel time domain signal samples.

21. The system as set forth in claim 18 above, wherein said time domain circuit includes an incremental circuit for generating the time domain signal samples as incremental time domain signal samples.

22. The system as set forth in claim 18 above, wherein said time domain circuit includes an incremental parallel input circuit for generating the time domain signal samples as incremental parallel time domain signal samples.

23. A transform processor system comprising:

a time domain circuit for generating time domain signal samples having a first resolution;

a transform processor for processing the time domain signal samples to generate frequency domain signal samples having a second resolution that is better than the first resolution of the time domain signal samples; and

a coherent post processor for coherently integrating the frequency domain signal samples generated with said transform processor.

24. A transform processor system comprising:

a time domain circuit for generating time domain signal samples;

a fast Fourier transform processor for processing the time domain signal samples to generate fast Fourier transforms, each fast Fourier transform having a plurality of frequency domain signal samples; and

a coherent post processor for coherently integrating the frequency domain signal samples, said post processor including an adder for adding each of the plurality of the frequency domain signal samples in one of the fast Fourier transforms generated with said fast Fourier transform processor to a corresponding one of the plurality of the frequency domain signal samples in a different one of the fast Fourier transforms generated with said fast Fourier trasnform processor to obtain a plurality of integrated frequency domain signal samples.

25. A transform processor system comprising:

a time domain circuit for generating time domain signal samples;

a transform processor for processing the time domain signal samples to generate frequency domain signal samples; and

a coherent frequency domain post processor for coherently integrating the frequency domain signal samples generated with said transform processor.

26. A transform processor system comprising:

an incremental time domain circuit for generating incremental time domain signal samples;

a transform processor for generating frequency domain signal samples by transforming the incremental time domain signal samples generated with said time domain circuit; and

a post processor for integrating the frequency domain signal samples to generate multi-bit digital whole number frequency domain signal samples.

27. The system as set forth in claim 26 above, wherein said incremental time domain circuit includes a charge coupled device for generating the incremental time domain signal samples as parallel incremental time domain signal samples, said charge coupled device including a serial input circuit for generating serial time domain input signal samples and a parallel output circuit for generating the parallel incremental time domain signal samples.

28. The system as set forth in claim 26 above, wherein said incremental time domain circuit includes an incremental parallel input circuit for generating the incremental time domain signal samples as incremental parallel time domain signal samples.

29. The system as set forth in claim 26 above, wherein said transform processor includes a processing gain circuit for generating the frequency domain signal samples with a multi-bit samples resolution that is better than the resolution of the incremental time domain signal samples.

30. The system as set forth in claim 26 above, wherein said incremental time domain circuit includes a complex incremental time domain circuit for generating complex incremental pairs of real and imaginary time domain signal samples, wherein said transform processor includes a complex signal processor for transform processing the incremental pairs of real and imaginary time domain signal samples to generate transforms, each transform having a plurality of pairs of real and imaginary frequency domain signal samples, and wherein said post processor includes a coherent integrator for coherently integrating the frequency domain signal samples.

31. A fast Fourier transform system comprising:

an incremental time domain circuit for generating incremental time domain signal samples;

an incremental fast Fourier transform processor for processing the incremental time domain signal samples that are generated with said parallel input circuit to generate fast Fourier transform, each fast Fourier transform having a plurality of frequency domain signal samples; and

a post processor for integrating the frequency domain signal samples to generate multi-bit digital whole number frequency domain signal samples.

32. A transform processor system comprising:

a time domain circuit for generating incremental time domain signal samples;

a transform processor for processing the incremental time domain signal samples to generate transforms, each transform having a plurality of incremental frequency domain signal samples; and

a post processor for integrating the incremental freqeuncy domain signal samples generated with said transform processor, said post processor including an adder for adding each of the incremental frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the incremental frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain an integrated transform of multi-bit digital whole number frequency domain samples.

33. A transform processor system comprising:

an incremental time domain circuit for generating pairs of real and imaginary incremental time domain signal samples;

a transform processor for processing the real and imaginary incremental time domain signal samples to generate transforms, each transform having a plurality of pairs of real and imaginary frequency domain signal samples; and

a post processor for integrating the pairs of real and imaginary frequency domain signal samples, said post processor including a real sample adder for adding each of the plurality of the frequency domain real signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the frequency domain real signal samples in a different one of the transforms generated with said transform processor and an imaginary sample adder for adding each of the plurality of the frequency domain imaginary signal samples in one of the transforms generated with said transform processor to a corresponding one of the plurality of the frequency domain imaginary signal samples in a different one of the transforms generated with said transforms processor to obtain a plurality of integrated pairs of real and imaginary multi-bit digital whole number frequency domain signal samples.

34. A transform processor system comprising:

a time domain circuit for generating pairs of real and imaginary incremental time domain signal samples;

a transform processor for transform processing the pairs of real and imaginary incremental time domain signal samples to generate transforms, each transform having a plurality of pairs of real and imaginary incremental frequency domain signal samples; and

a post processor for coherently integrating the frequency domain signal samples.

35. A transform processor system comprising:

a time domain circuit for generating pairs of real and imaginary incremental time domain signal samples;

a transform processor for processing the pairs of real and imaginary incremental time domain signal samples to generate transforms each transform having pairs of real and imaginary multi-bit digital whole number frequency domain signal samples; and

a post processor for coherently integrating the pairs of real and imaginary multi-bit digital whole number frequency domain signal samples generated with said transform processor;

said post processor including an adder for coherently adding each of the pairs of real and imaginary multi-bit digital whole number frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of a plurality of pairs of real and imaginary multi-bit digital whole number frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain a coherently integrated transform of pairs of real and imaginary multi-bit digital whole number frequency domain signal samples.

36. A transform processor system comprising:

an incremental time domain circuit for generating pairs of real and imaginary incremental time domain signal samples;

a transform processor for generating transforms of pairs of real and imaginary incremental frequency domain signal samples in response to the pairs of real and imaginary incremental time domain signal samples generated with said time domain circuit; and

a coherent integrator for coherently integrating the pairs of real and imaginary incremental frequency domain signal samples.

37. A transform processor system comprising:

an incremental time domain circuit for generating pairs of real and imaginary incremental time domain signal samples;

a transform processor for generating transforms of pairs of real and imaginary multi-bit digital whole number frequency domain signal samples in response to the pairs of real and imaginary incremental time domain siganl samples generated with said time domain circuit; and

a post processor for noncoherently integrating the pairs of real and imaginary multi-bit digital whole number frequency domain signal samples.

38. A transform processor system comprising:

an incremental time domain circuit for generating pairs of real and imaginary incremental time domain signal samples;

a transform processor for generating transforms of pairs of real and imaginary incremental frequency domain signal samples in response to the pairs of real and imaginary incremental time domain signal samples generated with said time domain circuit; and

a post processor for noncoherently integrating the pairs of real and imaginary incremental frequency domain signal samples generated with said transform processor.

39. A transform processor system comprising:

a time domain circuit for generating multi-bit digital whole number time domain signal samples having a first resolution;

a transform processor for generating multi-bit digital whole number frequency domain signal samples having a second resolution that is greater than the first resolution of the multi-bit digital whole number time domain signal samples in response to the first resolution multi-bit digital whole number time domain signal samples generated with said time domain circuit; and

a post processor for integrating the multi-bit digital whole number frequency domain signal samples having the second resolution to generate multi-bit digital whole number post processed signal samples having a third resolution that is greater than the second resolution of the multi-bit digital whole number frequency domain signal samples.

40. A transform processor system comprising:

a time domain circuit for generating multi-bit digital whole number time domain signal samples having a first resolution; and

a transform processor for processing the first resolution multi-bit digital whole number time domain signal samples from said time domain circuit to generate transforms of multi-bit digital whole number frequency domain signal samples having a second resolution that is greater than the first resolution of the multi-bit digital whole number time domain signal samples.

41. The system as set forth in claim 40 above, further comprising a post processor for integrating the multi-bit digital whole number frequency domain signal samples having the second resolution to generate multi-bit digial whole number post processed signal samples having a third resolution that is greater than the second resolution of the multi-bit digital whole number frequency domain signal samples.

42. A transform processor system comprising:

a time domain circuit for generating multi-bit digital time domain signal samples having a first resolution;

a transform processor for generating transforms of multi-bit digital frequency domain signal samples having a second resolution that is greater than the first resolution of the multi-bit digital time domain signal samples in response to the first resolution multi-bit digital time domain signal samples generated with said time domain circuit; and

a post processor for integrating the second resolution multi-bit digital frequency domain signal samples, said post processor including an adder for adding each of the second resolution multi-bit frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the second resolution multi-bit digital frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain a transform of integrated multi-bit digital whole number frequency domain signal samples.

43. A transform processor system comprising:

a time domain circuit for generating pairs of real and imaginary multi-bit digital time domain signal samples having a first resolution; and

a transform processor generating transforms of pairs of real and imaginary multi-bit digital frequency domain signal samples having a second resolution that is greater than the first resolution of the multi-bit digital time domain signal samples in response to the pairs of real and imaginary time domain signal samples generated with said time domain circuit.

44. A transform processor comprising:

a time domain circuit for generating pairs of real and imaginary multi-bit digital time domain signal samples having a first resolution;

a transform processor for generating transforms of pairs of real and imaginary multi-bit digital whole number frequency domain signal samples having a second reoslution that is greater than the first resolution of the multi-bit digital time domain signal samples in response to the pairs of real and imaginary first resolution multi-bit time domain signal samples generated with said time domain circuit; and

a post processor for coherently integrating the pairs of real and imaginary second resolution multi-bit digital whole number frequency domain signal samples, wherein said post processor includes an adder for coherently adding each of the pairs of real and imaginary second resolution multi-bit digital whole number frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the pairs of real and imaginary second resolution multi-bit digital whole number frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain a transform of coherently added pairs of real and imaginary multi-bit digital whole number frequency domain samples.

45. A transform processor system comprising:

a time domain circuit for generating pairs of real and imaginary multi-bit digital time domain signal samples having a first resolution;

a transform processor for generating transforms of pairs of real and imaginary multi-bit digital whole number frequency domain signal samples having a second resolution that is greater than the first resolution of the multi-bit digital time domain signal samples in response to the pairs of first resolution real and imaginary multi-bit digital time domain signal samples generated with said time domain circuit; and

a noncoherent post processor for noncoherently integrating the pairs of second resolution real and imaginary multi-bit digital whole number frequency domain signal samples, wherein said post processor includes an adder for noncoherently adding each of the pairs of second resolution real and imaginary multi-bit digital whole number frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the pairs of second resolution real and imaginary multi-bit digital whole number frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain noncoherently added pairs of real and imaginary multi-bit digital whole number frequency domain samples.

46. A transform processor system comprising:

a time domain circuit for generating time domain signal samples;

a transform processor for transforming the time domain signal samples from said time domain circuit to generate transforms, each transform having a plurality of frequency domain signal samples;

a post processor for integrating the frequency domain signal samples, said post processor including an adder for adding each of the frequency domain signal samples in one of the transforms generated with said transform processor to a corresponding one of the frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain a plurality of integrated frequency domain signal samples; and

a stored program digital computer for processing the integrated frequency domain signal samples that are generated with said post processor under control of a stored program.

47. A transform processor system comprising:

a time domain circuit for generating time domain signal samples;

a transform processor for transforming the time domain signal samples from said time domain circuit to generate transforms, each transform having a plurality of frequency domain signal samples;

a post processor for integrating the frequency domain signal samples, said post processor including an adder for adding each of the plurality of the frequency domain signal samples in one of the transforms generated with said transform processor to a correspnding one of the plurality of the frequency domain signal samples in a different one of the transforms generated with said transform processor to obtain a plurality of integrated frequency domain signal samples; and

a data link for communicating an integrated transform of frequency domain signal samples that are generated with said post processor to a remote location.

48. A transform processor system comprising:

a time domain circuit for generating time domain signal samples;

a transform processor for processing the time domain signal samples to generate transforms, each transform having a plurality of frequency domain signal samples generated in response to the time domain signal samples that are generated with said time domain circuit; and

a post processor for generating integrated signal samples by integrating the frequency domain signal samples.