Data processor execution unit which receives data with reduced instruction overhead

• US 4,744,043 A
• Filed: 03/25/1985
• Issued: 05/10/1988
• Est. Priority Date: 03/25/1985
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kloker, Kevin L.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/715,863
• Time in Patent Office: 1,142 Days
• Field of Search: 364/736, 364/716, 364/746
• US Class Current: 708/490
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing

Abstract

A data processor execution unit is provided for coupling multiple operands to an AU in response to an operand selection portion of an instruction supplied from an instruction register. At least two operands are provided from two pluralities of registers, respectively. Additionally, a predetermined one of the operands contains encoded information for selecting one of a plurality of arithmetic operations which the AU performs. The operand containing the encoded information is coupled to an AU control decoder for use in controlling the operation of the AU. In one form, a single operand selection portion of an instruction selects a plurality of registers containing operands which the AU may utilize. In another form, one of the operands contains encoded information for use in selecting arithmetic formats of the AU.

Claims

1. A data execution unit comprising:

an arithmetic unit (AU) for performing selected operations on first and second operands in one of a plurality of arithmetic formats and providing a resultant thereof;

an arithmetic unit control coupled to the arithmetic unit for selectively controlling the operation to be performed by said AU;

first means for providing said first operand to said arithmetic unit in response to an operand selection portion of an instruction;

second means for providing the second operand to said arithmetic unit, said second means providing the second operand to said arithmetic unit in response to the same operand selection portion of the instruction; and

third means for providing a third operand to said arithmetic unit in response to the same operand selection portion of the instruction, said third operand being used by the arithmetic unit control to select one of the plurality of arithmetic formats.

2. The data execution unit of claim 1 further comprising means for coupling the second means to the arithmetic unit control so that the second operand is also coupled to the arithmetic unit control in response to the same operand selection portion of the instruction, said second operand being used by the arithmetic unit control for selectively controlling, either solely or in combination with an operation portion of the instruction, the operation to be performed by said AU.

3. The data execution unit of claim 2 wherein the AU performs arithmetic operations on the first and third operands modulo the second operand.

4. The data execution unit of claim 2 wherein the first, second and third means each comprises a predetermined plurality of registers for storing the first, second and third operands, respectively.

5. A data execution unit comprising:

an arithmetic unit (AU) for performing selected operations on first and second operands in one of a plurality of arithmetic formats and providing a resultant thereof;

an arithmetic unit control coupled to the arithmetic unit for selectively controlling the operation to be performed by said AU;

first means coupled to the arithmetic unit for providing said first operand to said arithmetic unit in response to an operand selection portion of an instruction;

second means coupled to the arithmetic unit for providing said second operand; and

third means coupled to the arithmetic unit control for coupling a third operand to said arithmetic unit control in response to the operand selection portion of the instruction, said third operand selecting the arithmetic format of the arithmetic unit.

6. The data execution unit of claim 5 wherein the third means is further coupled to the arithmetic unit for also coupling the third operand to the arithmetic unit, said third operand being utilized by the arithmetic unit as a data operand in said selected operations.

7. A data execution unit comprising:

an arithmetic unit (AU) for performing a selected arithmetic operation on first and second operands in one of a plurality of arithmetic formats and providing a resultant thereof;

an arithmetic unit control for selecting an arithmetic operation to be performed by said AU in response to an operation portion of an instruction;

first means coupled to the arithmetic unit for providing the first operand to said arithmetic unit in response to a first operand selection portion of the instruction; and

second means coupled to the arithmetic unit for providing the second operand in response to a second operand selection portion of the instruction; and

third means coupled to the arithmetic unit control for providing a third operand in response to a third operand selection portion of the instruction, the third operand being used by the arithmetic unit control to select one of the plurality of arithmetic formats in which to execute the selected arithmetic operation.

8. The data execution unit of claim 7 further comprising means for coupling the third means to the arithmetic unit for selectively transmitting the third operand to the arithmetic unit in response to the third operand selection portion of the instruction.

9. The data execution unit of claim 8 wherein the first, second and third operand selection portions of the instruction are substantially the same portion of the instruction, thereby decreasing the size of the instruction.

10. The data execution unit of claim 8 wherein the AU performs arithmetic operations on first and second operands modulo the third operand.

11. The data execution unit of claim 8 wherein the first, second and third means each comprise a predetermined plurality of registers for storing said first, second and third operands, respectively.

12. In a data execution unit having an arithmetic unit (AU) for performing selected operations on first and second operands in one of a plurality of arithmetic formats in response to an arithmetic unit control and providing a resultant thereof, a method of selecting the arithmetic format in the AU, comprising the steps of:

storing the first operand in a first storage means and coupling the first operand to the AU in response to a first operand selection portion of an operating instruction;

storing the second operand in a second storage means and coupling the second operand to the AU in response to a second operand selection portion of the operating instruction;

storing a third operand in a third storage means and coupling the third operand to the arithmetic unit control in response to a third operand selection portion of the operating instruction;

using the third operand as an encoded arithmetic format signal; and

decoding the third operand to provide an arithmetic format control signal to the AU which selects the arithmetic format of the selected operations executed by the AU.

13. The method of claim 12 wherein said first, second and third operand selection portions of the operating instruction are substantially the same portion of the instruction.