Hardware modeling system and method for simulating portions of electrical circuits
First Claim
1. In a simulation system which includes plural workstations for independently and simultaneously simulating the response of electronic circuits to applied test data, a hardware modeling system for simulating the response of a plural pin circuit element by evaluating the behavior of an actual circuit element upon recognition by a workstation that the circuit element in an electronic circuit being simulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the hardware modeling system comprising:
- hardware modeling circuit means including input means for receiving input test data from the workstation, stimulus signal generation means coupled to the input means for converting the input test data into evaluation stimuli corresponding to the input test data, application means coupled to the stimulus signal generation means for applying the evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled coupled to the actual circuit element for receiving output signals from the actual circuit element and for converting the output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli, and output means coupled to the retrieval means for receiving the resultant test data; and
network interface means for coupling the plural workstations to the hardware modeling circuit means so as to provide concurrent access by each of the workstations to the hardware modeling circuit means, said network interface means comprising means for coupling the workstations to the input means and for transferring input test data from a workstation to the input means upon recognition that the plural pin circuit element being stimulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the network interface means also comprising means coupling the output means to the workstations and for transfering resultant test data from the output means to the workstation following completion of a simulation, the network interface means thereby comprising means for interfacing the workstations to the hardware modeling circuit means so as to permit sharing of the hardware modeling circuit means among the workstations for concurrent circuit simulations by the workstations.
0 Assignments
0 Petitions
Accused Products
Abstract
A hardware modeling system 10 simulates portions of electrical circuits 16, 18 utilizing actual hardware components in the simulation. Access to these hardware modeling elements 16, 18 is provided on a shared basis to plural workstations 14. Simulation vectors for plural users may be stored discontiguously in a first memory 26 and a single user'"'"'s vectors are transferred to a second memory 28 for streaming to the elements 16, 18. An optional timing analyzer and memory circuit 34 periodically samples outputs from pins of the hardware modeling elements to provide timing information on the response of such elements. High impedance testing and bus contention detection is performed on the pins of the hardware modeling elements. Clocking signals applied to the hardware modeling elements are adjustable and may be set at extremely high frequencies. A special gating circuit 292 accesses each pin of the hardware modeling elements and incorporates one or more of the above features.
-
Citations
38 Claims
-
1. In a simulation system which includes plural workstations for independently and simultaneously simulating the response of electronic circuits to applied test data, a hardware modeling system for simulating the response of a plural pin circuit element by evaluating the behavior of an actual circuit element upon recognition by a workstation that the circuit element in an electronic circuit being simulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the hardware modeling system comprising:
-
hardware modeling circuit means including input means for receiving input test data from the workstation, stimulus signal generation means coupled to the input means for converting the input test data into evaluation stimuli corresponding to the input test data, application means coupled to the stimulus signal generation means for applying the evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled coupled to the actual circuit element for receiving output signals from the actual circuit element and for converting the output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli, and output means coupled to the retrieval means for receiving the resultant test data; and network interface means for coupling the plural workstations to the hardware modeling circuit means so as to provide concurrent access by each of the workstations to the hardware modeling circuit means, said network interface means comprising means for coupling the workstations to the input means and for transferring input test data from a workstation to the input means upon recognition that the plural pin circuit element being stimulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the network interface means also comprising means coupling the output means to the workstations and for transfering resultant test data from the output means to the workstation following completion of a simulation, the network interface means thereby comprising means for interfacing the workstations to the hardware modeling circuit means so as to permit sharing of the hardware modeling circuit means among the workstations for concurrent circuit simulations by the workstations. - View Dependent Claims (2, 3, 4)
-
- 5. A hardware modeling system with a plurality of different plural pin hardware modeling elements used for performing simulations of the performance of electronic circuits in response to input test data, means for converting test data to evaluation stimuli and for applying the evaluation stimuli to selected input pins of the hardware modeling element, means for retrieving output signals from selected output pins of the hardware modeling element and for converting the output signals to resultant test data, timing analyzer circuit means for periodically sampling the resultant data from the output pins to provide a timing representation of the resultant data at the output pins over time, and means for selectively coupling the timing analyzer circuit means to the output pins to provide the timing representation.
-
7. In a hardware modeling system in which evaluation stimuli corresponding to data signals and clocking signals are applied to pins of a plurality of different plural pin hardware modeling elements used in circuit simulations so as to produce output signals from output pins of the hardware modeling elements and thereby simulation results;
-
gating circuit means with plural circuit pin connections, each such pin connection for connection to a single associated pin of a hardware modeling element; means for selecting any of the pin connections as input data pin connections; means for transferring test stimuli to the input data pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as clock pin connections; means for transferring clocking signals to the clock pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as output data connections; and means for receiving output data from the output data connections and thereby from the associated pins of the hardware modeling element. - View Dependent Claims (8, 9, 10)
-
-
11. A hardware modeling system in which evaluation stimuli corresponding to data signals and clocking signals are applied to pins of a plural pin hardware modeling element corresponding to a component in a circuit being simulated so as to produce output signals from output pins of the hardware modeling element for use in the circuit stimulation, the system including;
-
gating circuit means with plural circuit pin connections, each such pin connection for connection to a single associated pin of a hardware modeling element; means for selecting any of the pin connections as input data pin connections; means for transferring test stimuli to the input data pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as clock pin connections; means for transferring clocking signals to the clock pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as output data connections; means for receiving output data from the output data connections and thereby from the associated pins of the hardware modeling element; the system further including bus contention detection means for indicating when any of such pin connections are driven by a signal from a hardware modeling element to one state while the same pin connection is driven by a signal from the gating circuit to an opposite state, and for disabling at least one of the drive signals applied to the pin connection under such conditions. - View Dependent Claims (12, 13)
-
-
14. A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising:
-
memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retriveval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli to the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; and the memory means including first memory means for receiving and storing input test data from the workstation for plural circuit simulations, second memory means for receiving input test data from the first memory means for a single simulation, the control circuit means comprising means for controlling the transfer of input test data for a simulation from the second memory means to the circuit interface means and for controlling the transfer of input test data for a single simulation from the first memory means to the second memory means following the transfer from the second memory means to the circuit interface means. - View Dependent Claims (15, 16, 17, 18, 19, 20, 22, 23)
-
-
21. A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising:
-
memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retrieval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli to the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; the memory means including first memory means for receiving and storing input test data from the workstation for plural circuit simulations, second memory means for receiving input test data from the first memory means for a single simulation, the control circuit means comprising means for controlling the transfer of input test data for a simulation from the second memory means to the circuit interface means and for controlling the transfer of input test data for a single simulation from the first memory means to the second memory means following the transfer from the second memory means to the circuit interface means; and the memory means including third supplemental disk memory means which acts as a virtual memory means, the hardware modeling system including means for swapping inputting test data from the first to third memory means and from the third to first memory means. - View Dependent Claims (24, 25)
-
-
26. A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising:
-
memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retrieval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli by the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; the control circuit means including first clock means for clocking a first set of input test data from the memory means to the circuit interface means, second clock means for clocking a second set of input test data from the memory means to the circuit interface means, master clock means for generating master clock signals for clocking the stimulus signal generation means following the transfers of the first and second sets of input test data, thereby controlling the generation of evaluation stimuli to correspond to both of the first and second sets of input test data, and device clock means for generating device clock signals for clocking the actual circuit elements. - View Dependent Claims (27)
-
-
28. A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising:
-
memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retreval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli by the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; the system further including bus contention means for detcting bus contentions, a bus contention occurring upon the application of a drive signal by the application means to a pin of the actual circuit element simultaneously with the generation of an output drive signal at such pin by the actual circuit element in response to the applied evaluation stimuli. - View Dependent Claims (29)
-
-
30. An electronic circuit simulation method in which actual plural pin hardware circuit elements are used in the simulation comprising:
-
storing test data for plural simulations in a first memory; transferring test data for a single simulation from the first memory to a second memory; applying test data for the single simulation from the second memory to an actual hardware circuit element to provide resultant test data from the circuit element; and transferring test data for successive single simulations from the first memory to the second memory following the application of test data for a prior single simulation to an actual hardware modeling element. - View Dependent Claims (31, 32)
-
-
33. In a simulation system which includes plural workstations for simulating the response of electronic circuits to applied test data, a hardware modeling system for simulating the response of at least one plural pin circuit element by evaluating the behavior of an actual circuit element upon recognition by a workstation that the circuit element in an electronic circuit being simulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the hardware modeling system comprising:
-
hardware modeling circuit means including input means for receiving input test data from the workstations, stimulus signal generation means coupled to the input means for converting the input test data into evaluation stimuli corresponding to the input test data, application means coupled to the stimulus signal generation means for applying the evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and for converting the output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli, and output means coupled to the retrieval means for receiving the resultant test data; network interface means for coupling the plural workstations to the hardware modeling circuit means so as to provide access by each of the workstations to the hardware modeling circuit means, said network interface means comprising means for coupling the workstations to the input means and for transferring input test data from a workstation to the input means upon recognition that the plural pin circuit element being stimulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the network interface means also comprising means coupling the output means to the workstations and for transferring resultant test data from the output means to the workstation following completion of a simulation, the network interface means thereby comprising means for interfacing the workstations to the hardware modeling circuit means so as to permit sharing of the hardware modeling circuit means among the workstations; and the hardware modeling circuit means including; user memory means for storing input test data for one or more simulations; operating memory means for storing input test data for only one simulation; means for applying input test data from the operating memory means to said means for converting test data during a simulation; and means for transferring input test data for a single simulation from the user memory means to the operating memory means following the application of input test data for a prior simulation from the operating memory means to the means for converting test data. - View Dependent Claims (34, 35, 36)
-
-
37. A simulation system comprising:
-
plural workstations each capable of independently performing circuit evaluations of various circuit in which the evaluations involve at least in part a software simulation of the circuit being evaluated by each workstation; hardware modeling circuit means coupled to the plural workstations and including at least one actual circuit element, the hardware modeling circuit means comprising means for providing shared access by the plural workstations to the actual circuit element, the hardware modeling circuit means comprsing means permitting the plural workstations to perform concurrent circuit evaluations using the actual hardware element in the evaluation when such element appears in the circuits being evaluated by the plural workstations. - View Dependent Claims (38)
-
Specification