BPSK demodulator with D type flip/flop

• US 4,744,094 A
• Filed: 12/12/1986
• Issued: 05/10/1988
• Est. Priority Date: 12/12/1986
• Status: Expired due to Fees

• Current Assignee: Zenith Electronics Corporation (LG Corporation)
• Original Assignee: Zenith Electronics Corporation (LG Corporation)
• Inventors: McCarren, Daniel S.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/940,822
• Time in Patent Office: 515 Days
• Field of Search: 375/80, 375/81, 375/83, 329/104, 329/110, 329/124, 329/105, 328/72, 328/133, 360/51, 307/269
• US Class Current: 375/327
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

A BPSK demodulator includes a D type flip-flop having a clock terminal supplied with the output of a phase locked loop (PLL). The ouput of the D flip-flop and the carrier are provided as inputs to an exclusive OR gate, the output of which is used to lock up the PLL. The VCO in the PLL is phase displaced 90° with respect to the carrier such that the carrier is sampled to detect the data.

Claims

1. A BPSK demodulator comprising:

means receiving a carrier modulated with data in BPSK form;

a PLL source of clock signal that is 90°

displaced with respect to said carrier;

demodulation means comprising a D flip-flop having one input for receiving said carrier, another input for receiving said clock signal and an output for producing said data; and

gate means supplied with said data and with said carrier for supplying a locking signal to said PLL.

2. The demodulator of claim 1, wherein said gate means includes an exclusive OR gate receiving inputs of said carrier and said data and supplying an output to said PLL.

3. The demodulator of claim 2, further including a lock detector having inputs supplied by said exclusive OR gate and said PLL and being coupled to control operation of said D flip-flop.

4. A BPSK demodulator comprising:

means receiving a carrier modulated with data in BPSK form;

a PLL source of clock signal that is 90°

phase displaced with respect to said carrier;

a demodulator including a D flip-flop having one input receiving said carrier, another input receiving said clock signal and an output producing said data; and

an exclusive OR gate supplied with said data and with said carrier for supplying a locking signal to said PLL.

5. The demodulator of claim 4, further including a lock detector having inputs supplied by said exclusive OR gate and said PLL and being coupled to control operation of said D flip-flop.